Suppressing device variability by cryogenic implant for 28-nm low-power SoC applications

C. L. Yang; C. H. Tsai; C. I. Li; C. Y. Tzeng; G. P. Lin; W. J. Chen; Y. L. Chin; C. I. Liao; M. Chan; J. Y. Wu; E. R. Hsieh; B. N. Guo; S. Lu; B. Colombeau; S. S. Chung; I. C. Chen

doi:10.1109/LED.2012.2209395

Suppressing device variability by cryogenic implant for 28-nm low-power SoC applications

C. L. Yang, C. H. Tsai, C. I. Li, C. Y. Tzeng, G. P. Lin, W. J. Chen, Y. L. Chin, C. I. Liao, M. Chan, J. Y. Wu, E. R. Hsieh, B. N. Guo, S. Lu, B. Colombeau, S. S. Chung, I. C. Chen

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

In this letter, we have demonstrated that cryogenic implant in the source and drain formation offers advantages for reducing the threshold voltage mismatch in pMOSFET. A discrete dopant profiling method is used to verify the presence of boron out-diffusion from the drain, which further induces the random dopant fluctuation. Results show that this boron out-diffusion can be greatly reduced in this new process. Two major factors in improving the device variability by cryogenic implant are discussed, i.e., the polysilicon grain size control and the embedded-SiGe dislocation defect reduction during source and drain formation.

Original language	English
Article number	6289339
Pages (from-to)	1444-1446
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	33
Issue number	10
DOIs	https://doi.org/10.1109/LED.2012.2209395
State	Published - 2012

Keywords

Cryogenic implant
ion implantation
logic device
novel process technology
random dopant fluctuation

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10.1109/LED.2012.2209395

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Yang, C. L., Tsai, C. H., Li, C. I., Tzeng, C. Y., Lin, G. P., Chen, W. J., Chin, Y. L., Liao, C. I., Chan, M., Wu, J. Y., Hsieh, E. R., Guo, B. N., Lu, S., Colombeau, B., Chung, S. S., & Chen, I. C. (2012). Suppressing device variability by cryogenic implant for 28-nm low-power SoC applications. IEEE Electron Device Letters, 33(10), 1444-1446. [6289339]. https://doi.org/10.1109/LED.2012.2209395

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abstract = "In this letter, we have demonstrated that cryogenic implant in the source and drain formation offers advantages for reducing the threshold voltage mismatch in pMOSFET. A discrete dopant profiling method is used to verify the presence of boron out-diffusion from the drain, which further induces the random dopant fluctuation. Results show that this boron out-diffusion can be greatly reduced in this new process. Two major factors in improving the device variability by cryogenic implant are discussed, i.e., the polysilicon grain size control and the embedded-SiGe dislocation defect reduction during source and drain formation.",

keywords = "Cryogenic implant, ion implantation, logic device, novel process technology, random dopant fluctuation",

author = "Yang, {C. L.} and Tsai, {C. H.} and Li, {C. I.} and Tzeng, {C. Y.} and Lin, {G. P.} and Chen, {W. J.} and Chin, {Y. L.} and Liao, {C. I.} and M. Chan and Wu, {J. Y.} and Hsieh, {E. R.} and Guo, {B. N.} and S. Lu and B. Colombeau and Chung, {S. S.} and Chen, {I. C.}",

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T1 - Suppressing device variability by cryogenic implant for 28-nm low-power SoC applications

AU - Yang, C. L.

AU - Tsai, C. H.

AU - Li, C. I.

AU - Tzeng, C. Y.

AU - Lin, G. P.

AU - Chen, W. J.

AU - Chin, Y. L.

AU - Liao, C. I.

AU - Chan, M.

AU - Wu, J. Y.

AU - Hsieh, E. R.

AU - Guo, B. N.

AU - Lu, S.

AU - Colombeau, B.

AU - Chung, S. S.

AU - Chen, I. C.

PY - 2012

Y1 - 2012

N2 - In this letter, we have demonstrated that cryogenic implant in the source and drain formation offers advantages for reducing the threshold voltage mismatch in pMOSFET. A discrete dopant profiling method is used to verify the presence of boron out-diffusion from the drain, which further induces the random dopant fluctuation. Results show that this boron out-diffusion can be greatly reduced in this new process. Two major factors in improving the device variability by cryogenic implant are discussed, i.e., the polysilicon grain size control and the embedded-SiGe dislocation defect reduction during source and drain formation.

AB - In this letter, we have demonstrated that cryogenic implant in the source and drain formation offers advantages for reducing the threshold voltage mismatch in pMOSFET. A discrete dopant profiling method is used to verify the presence of boron out-diffusion from the drain, which further induces the random dopant fluctuation. Results show that this boron out-diffusion can be greatly reduced in this new process. Two major factors in improving the device variability by cryogenic implant are discussed, i.e., the polysilicon grain size control and the embedded-SiGe dislocation defect reduction during source and drain formation.

KW - Cryogenic implant

KW - ion implantation

KW - logic device

KW - novel process technology

KW - random dopant fluctuation

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M3 - 期刊論文

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VL - 33

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EP - 1446

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 10

M1 - 6289339

ER -

Suppressing device variability by cryogenic implant for 28-nm low-power SoC applications

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Keywords

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