Abstract
In this paper, a new circuit interconnection scheme of the low-power current-sensing complementary pass-transistor logic (LCSCPTL) is proposed and analyzed. The proposed new circuit scheme using full-swing and non-full-swing output signals to control the NMOS pass transistor logic tree network. Due to the non-full-swing outputs and the current-sensing scheme, the new logic circuit scheme can improve the power dissipation and operation speed. The non-full-swing LCSCPTL is applied to the design of the parallel multiplier. The 4-2 compressors and the conditional carry selection scheme are used in this design to achieve regular layout and improve the operation speed. Moreover, the 1.2 V 8*8-bit parallel multiplier can be fabricated without changing the conventional 5 V CMOS process. The operation speed of the parallel multiplier is 32 ns for 1.2 v supply voltage.
| Original language | English |
|---|---|
| Pages (from-to) | 1948-1951 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 3 |
| State | Published - 1997 |
| Event | Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong Duration: 9 Jun 1997 → 12 Jun 1997 |