Sub-60 mV/dec ferroelectric HZO MoS2 negative capacitance field-effect transistor with internal metal gate: The role of parasitic capacitance

M. Si, C. Jiang, C. J. Su, Y. T. Tang, L. Yang, W. Chung, M. A. Alam, P. D. Ye

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

24 Scopus citations

Abstract

Steep-slope MoS2 NC-FETs with ferroelectric HZO and internal metal gate in the gate dielectric stack are demonstrated. SS less than 50 mV/dec is obtained for both forward and reverse gate voltage sweeps, with minimum SSFor = 37.6 mV/dec and minimum SSRev = 42.2 mV/dec. A second minimum of SSRev as low as 8.3 mV/dec can be measured as the result of dynamic switching at high speed in ferroelectric HZO. The impact of parasitic capacitance on SS and dynamic hysteresis is systematically studied by both experiment and dynamic simulation.

Original languageEnglish
Title of host publication2017 IEEE International Electron Devices Meeting, IEDM 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages23.5.1-23.5.4
ISBN (Electronic)9781538635599
DOIs
StatePublished - 23 Jan 2018
Event63rd IEEE International Electron Devices Meeting, IEDM 2017 - San Francisco, United States
Duration: 2 Dec 20176 Dec 2017

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference63rd IEEE International Electron Devices Meeting, IEDM 2017
Country/TerritoryUnited States
CitySan Francisco
Period2/12/176/12/17

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