Sub-60 mV/dec ferroelectric HZO MoS2 negative capacitance field-effect transistor with internal metal gate: The role of parasitic capacitance

M. Si; C. Jiang; C. J. Su; Y. T. Tang; L. Yang; W. Chung; M. A. Alam; P. D. Ye

doi:10.1109/IEDM.2017.8268447

Sub-60 mV/dec ferroelectric HZO MoS₂ negative capacitance field-effect transistor with internal metal gate: The role of parasitic capacitance

M. Si, C. Jiang, C. J. Su, Y. T. Tang, L. Yang, W. Chung, M. A. Alam, P. D. Ye

College of Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

27 Scopus citations

Abstract

Steep-slope MoS₂ NC-FETs with ferroelectric HZO and internal metal gate in the gate dielectric stack are demonstrated. SS less than 50 mV/dec is obtained for both forward and reverse gate voltage sweeps, with minimum SS_For = 37.6 mV/dec and minimum SS_Rev = 42.2 mV/dec. A second minimum of SS_Rev as low as 8.3 mV/dec can be measured as the result of dynamic switching at high speed in ferroelectric HZO. The impact of parasitic capacitance on SS and dynamic hysteresis is systematically studied by both experiment and dynamic simulation.

Original language	English
Title of host publication	2017 IEEE International Electron Devices Meeting, IEDM 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	23.5.1-23.5.4
ISBN (Electronic)	9781538635599
DOIs	https://doi.org/10.1109/IEDM.2017.8268447
State	Published - 23 Jan 2018
Event	63rd IEEE International Electron Devices Meeting, IEDM 2017 - San Francisco, United States Duration: 2 Dec 2017 → 6 Dec 2017

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Conference

Conference	63rd IEEE International Electron Devices Meeting, IEDM 2017
Country/Territory	United States
City	San Francisco
Period	2/12/17 → 6/12/17

Access to Document

10.1109/IEDM.2017.8268447

Cite this

Si, M., Jiang, C., Su, C. J., Tang, Y. T., Yang, L., Chung, W., Alam, M. A., & Ye, P. D. (2018). Sub-60 mV/dec ferroelectric HZO MoS₂ negative capacitance field-effect transistor with internal metal gate: The role of parasitic capacitance. In 2017 IEEE International Electron Devices Meeting, IEDM 2017 (pp. 23.5.1-23.5.4). (Technical Digest - International Electron Devices Meeting, IEDM). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2017.8268447

Si, M. ; Jiang, C. ; Su, C. J. et al. / Sub-60 mV/dec ferroelectric HZO MoS₂ negative capacitance field-effect transistor with internal metal gate : The role of parasitic capacitance. 2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 23.5.1-23.5.4 (Technical Digest - International Electron Devices Meeting, IEDM).

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abstract = "Steep-slope MoS2 NC-FETs with ferroelectric HZO and internal metal gate in the gate dielectric stack are demonstrated. SS less than 50 mV/dec is obtained for both forward and reverse gate voltage sweeps, with minimum SSFor = 37.6 mV/dec and minimum SSRev = 42.2 mV/dec. A second minimum of SSRev as low as 8.3 mV/dec can be measured as the result of dynamic switching at high speed in ferroelectric HZO. The impact of parasitic capacitance on SS and dynamic hysteresis is systematically studied by both experiment and dynamic simulation.",

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Si, M, Jiang, C, Su, CJ, Tang, YT, Yang, L, Chung, W, Alam, MA & Ye, PD 2018, Sub-60 mV/dec ferroelectric HZO MoS₂ negative capacitance field-effect transistor with internal metal gate: The role of parasitic capacitance. in 2017 IEEE International Electron Devices Meeting, IEDM 2017. Technical Digest - International Electron Devices Meeting, IEDM, Institute of Electrical and Electronics Engineers Inc., pp. 23.5.1-23.5.4, 63rd IEEE International Electron Devices Meeting, IEDM 2017, San Francisco, United States, 2/12/17. https://doi.org/10.1109/IEDM.2017.8268447

Sub-60 mV/dec ferroelectric HZO MoS₂ negative capacitance field-effect transistor with internal metal gate: The role of parasitic capacitance. / Si, M.; Jiang, C.; Su, C. J. et al.
2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 23.5.1-23.5.4 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - Steep-slope MoS2 NC-FETs with ferroelectric HZO and internal metal gate in the gate dielectric stack are demonstrated. SS less than 50 mV/dec is obtained for both forward and reverse gate voltage sweeps, with minimum SSFor = 37.6 mV/dec and minimum SSRev = 42.2 mV/dec. A second minimum of SSRev as low as 8.3 mV/dec can be measured as the result of dynamic switching at high speed in ferroelectric HZO. The impact of parasitic capacitance on SS and dynamic hysteresis is systematically studied by both experiment and dynamic simulation.

AB - Steep-slope MoS2 NC-FETs with ferroelectric HZO and internal metal gate in the gate dielectric stack are demonstrated. SS less than 50 mV/dec is obtained for both forward and reverse gate voltage sweeps, with minimum SSFor = 37.6 mV/dec and minimum SSRev = 42.2 mV/dec. A second minimum of SSRev as low as 8.3 mV/dec can be measured as the result of dynamic switching at high speed in ferroelectric HZO. The impact of parasitic capacitance on SS and dynamic hysteresis is systematically studied by both experiment and dynamic simulation.

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Si M, Jiang C, Su CJ, Tang YT, Yang L, Chung W et al. Sub-60 mV/dec ferroelectric HZO MoS₂ negative capacitance field-effect transistor with internal metal gate: The role of parasitic capacitance. In 2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc. 2018. p. 23.5.1-23.5.4. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2017.8268447