Structural fault based specification reduction for testing analog circuits

Soon Jyh Chang, Chung Len Lee, Jwu E. Chen

Research output: Contribution to journalArticlepeer-review

8 Scopus citations


Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is proposed and demonstrated. It starts with first deriving relationships between specifications and parameter variations of the circuit-under-test (CUT) and then reduces specifications by considering bounds of parameter variations. A statistical approach by taking into account of circuit fabrication process fluctuation is also employed and the result shows that the specification reduction depends on the testing confidence. A continuous-time state-variable benchmark filter circuit is applied with this methodology to demonstrate the effectiveness of the approach.

Original languageEnglish
Pages (from-to)571-581
Number of pages11
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Issue number6
StatePublished - Dec 2002


  • Analog test
  • Fault-based test
  • Specification-based test
  • Test cost reduction


Dive into the research topics of 'Structural fault based specification reduction for testing analog circuits'. Together they form a unique fingerprint.

Cite this