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Dynamic random access memory (DRAM) is one key component in modern electronic systems. In this paper, we propose a software-hardware-cooperated built-in self-test (SHC-BIST) scheme for the channel-based DRAMs. The testing of DRAMs consists of two major phases: DRAM initialization and DRAM array testing. Typically, the DRAM initialization process is short and executed in the beginning of the DRAM array testing. Thus, it is inefficient to realize it using the dedicated BIST hardware. On the other hand, it is not time efficient if we use the processor (software) to execute the DRAM array testing. Therefore, the SHC-BIST scheme uses a programmable BIST circuit to execute the DRAM array testing and takes advantage of the processor to execute the DRAM initialization and control the programmable BIST circuit such that the test time and hardware cost can be minimized. We verify the SHC-BIST scheme using a system with a LEON3 processor and a multi-channel DRAM.
|Title of host publication||ITC-Asia 2017 - International Test Conference in Asia|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||5|
|State||Published - 3 Nov 2017|
|Event||1st International Test Conference in Asia, ITC-Asia 2017 - Taipei, Taiwan|
Duration: 13 Sep 2017 → 15 Sep 2017
|Name||ITC-Asia 2017 - International Test Conference in Asia|
|Conference||1st International Test Conference in Asia, ITC-Asia 2017|
|Period||13/09/17 → 15/09/17|
- built-in self-test
- channel-based DRAM
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- 1 Finished
1/08/17 → 31/07/18