Single-fault fault collapsing analysis in sequential logic circuits

Jwu E. Chen, Chung Len Lee, Wen Zen Shen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations


A study of fault collapsing for synchronous sequential circuits is presented. Two phenomena, self-hiding and delay-reconvergence, which invalidate the combinational fault dominance relationship in sequential circuits are identified. These phenomena are caused by the existence of feedback paths and storage elements in sequential circuits. From this analysis, a single-fault fault-collapsing procedure for synchronous irredundant sequential circuits is proposed to reduce the faults for which test has to be generated. This procedure can be applied not only to a nonscan mode circuit, but also to a full-scan and a partial-scan mode circuit by cutting the inputs and outputs of scannable D flip-flops as the primary outputs and inputs of the circuit, respectively. This procedure has been applied to collapse faults for the 31 benchmark sequential circuits, and a 57% reduction in the number of faults as compared with the total number of original faults has been obtained.

Original languageEnglish
Title of host publicationDigest of Papers - International Test Conference
PublisherPubl by IEEE
Number of pages6
ISBN (Print)0818620641
StatePublished - Sep 1990
EventProceedings - International Test Conference 1990 - Washington, DC, USA
Duration: 10 Sep 199014 Sep 1990

Publication series

NameDigest of Papers - International Test Conference
ISSN (Print)0743-1686


ConferenceProceedings - International Test Conference 1990
CityWashington, DC, USA


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