Single-Fault Fault-Collapsing Analysis in Sequential Logic Circuits

Jwu E. Chen, Chung Len Lee, Wen Zen Shen

Research output: Contribution to journalArticlepeer-review

12 Scopus citations


This paper studies single-fault fault collapsing in sequential logic circuits. Two major phenomena, self-hiding (SH) and delayed reconvergence (DR), which arise from the existence of feedback paths and storage elements in sequential circuits, are analyzed and found to cause the dominance relationship which is valid in combinational circuits but no longer valid in sequential circuits. A fault-collapsing procedure is proposed to collapse faults in sequential circuits. It first collapses faults in the non-SAD (self-hiding and delayed-reconvergence) gates of the combinational part of the sequential circuit and then further collapses faults by identifying the prime fan-out branches. Finally, it collapses faults in feedback lines. The collapsed faults constitute a sufficient representative set of prime faults. This procedure has been applied to collapse faults for 31 benchmark sequential circuits [1] and the number of faults has collapsed to 43% of the original number.

Original languageEnglish
Pages (from-to)1559-1568
Number of pages10
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number12
StatePublished - Dec 1991


Dive into the research topics of 'Single-Fault Fault-Collapsing Analysis in Sequential Logic Circuits'. Together they form a unique fingerprint.

Cite this