Single chip implementation of the 1.6 Kbps speech vocoder

Jia Ching Wang, Jhing Fa Wang, Han Chiang Chen

Research output: Contribution to journalConference articlepeer-review

3 Scopus citations

Abstract

In this paper, we propose a low bit rate speech vocoder and its corresponding VLSI implementation. The vocoder exploits the interpolation property so that the fine quality in synthesized speech is obtained even though the bit rate is as low as 1.6 Kbps. Two novel methods including pitch detection and LSP decoding which are suitable for VLSI implementation are also proposed. The heuristic pitch detection algorithm avoids the heavy computational load introduced by the traditional normalized autocorrelation method. The memory storing triangular function value is no longer needed after adopting the new LSP decoding process. The chip is designed with area effective feature and is suitable for stand alone application.

Original languageEnglish
Pages (from-to)V-597-V-600
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume5
StatePublished - 2000
EventProceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems - Geneva, Switz
Duration: 28 May 200031 May 2000

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