Simultaneous floorplanning and buffer block planning

I. Hui-Ru Jiang, Yao Wen Chang, Jing Yang Jou, Kai Yuan Chao

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

As technology advances and the number of interconnections among modules rapidly increases, timing closure and design convergence are the most important concerns. Hence, it is desirable to consider interconnect optimization as early as possible. In this paper, we first address simultaneous floorplanning and buffer block planning (i.e., integrating buffer block planning into floorplanning) for interconnect optimization. Experimental results show that our method can significantly improve the interconnect delay and reduce the number of buffers needed.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages431-434
Number of pages4
ISBN (Electronic)0780376595
DOIs
StatePublished - 2003
EventAsia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan
Duration: 21 Jan 200324 Jan 2003

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2003-January

Conference

ConferenceAsia and South Pacific Design Automation Conference, ASP-DAC 2003
Country/TerritoryJapan
CityKitakyushu
Period21/01/0324/01/03

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