A silicon compiler system for layout generation from generalized register-transfer schematics is described. This system uses the SLAM floorplan compiler and the ICDB component server with parameterizable bit-sliced and glue-logic generators. The SLAM compiler partitions the netlist into component sets best suited for different layout styles, such as bit-sliced or strip-oriented logic. Based on a stripped and sliced layout architecture, each component set is partitioned further into clusters to achieve better floorplanning. The ICDB component server is capable of optimizing logic and producing layouts for the component sets according to performance constraints. The component server provides layouts with different aspect ratios and I/O pin locations for better floorplanning. Several experiments demonstrate that highly dense layouts can be achieved using this system.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1990|
|Event||1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA|
Duration: 1 May 1990 → 3 May 1990