Self-sampled vernier delay line for built-in clock jitter measurement

Kuo Hsing Cheng, Chan Wei Huang, Shu Yu Jiang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

For high-speed analog and mixed signal circuits, on-chip clock jitter measurement has been a challenge in recent years. Circuit resolution, chip area, and frequency range are critical specification for built-in-test (BIT) circuit design. In order to fulfill these requirements, the self-sampled vernier delay line (VDL) structure is proposed. Comparing with traditional VDL structure, there is no more jitter free sample clock used in this design. When the proposed circuit is designed in 14ps circuit resolution, only 500um*750um chip area is used for 100MHz to 400MHz measurement range in TSMC 0.35um CMOS process.

Original languageEnglish
Title of host publicationISCAS 2006
Subtitle of host publication2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages1591-1594
Number of pages4
StatePublished - 2006
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
Duration: 21 May 200624 May 2006

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

ConferenceISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Country/TerritoryGreece
CityKos
Period21/05/0624/05/06

Fingerprint

Dive into the research topics of 'Self-sampled vernier delay line for built-in clock jitter measurement'. Together they form a unique fingerprint.

Cite this