Aggressive technology scaling trends, such as thinner gate oxide without proportional downscaling of supply voltage, aggravate the aging impact and thus necessitate an aging-aware reliability verification and optimization framework during early design stages. In this paper, we propose a novel in-situ sensing strategy based on deploying transition detectors (TDs), for on-chip aging monitoring and resilience. Transformed into the set cover problem and then formulated into maximum satisfiability, the proposed problem of TD/sensor placement can be solved efficiently. Experimental results show that, by introducing at most 2.2% area overhead (for TD/sensor placement), the aging behavior of a target circuit can be effectively monitored, and the correctness of its functionality can be perfectly guaranteed with an average of 77% aging resilience achieved. In other words, with 2.2% area overhead, potential aging-induced timing errors can be detected and then eliminated, while achieving 77% recovery from aging-induced performance degradation.