Inductance effects on on-chip interconnects have become more and more significant in today's high-speed digital circuits, especially on global interconnects such as signal buses. However, most existing works consider only RC effects, e.g., the worst-case switching pattern resulting from coupling capacitance, to develop their encoding schemes to reduce bus delay. In this paper, we show that the worst-case switching patterns that incur the largest bus delay are completely different while considering RC and RLC effects. The finding implies that existing encoding schemes based on RC model might not improve or even worsen the bus delay when inductance effects become dominant.
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 2004|
|Event||2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada|
Duration: 23 May 2004 → 26 May 2004