RLC effects on worst-case switching pattern for on-chip buses

Shang Wei Tu, Jing Yang Jou, Yao Wen Chang

Research output: Contribution to journalConference articlepeer-review

10 Scopus citations


Inductance effects on on-chip interconnects have become more and more significant in today's high-speed digital circuits, especially on global interconnects such as signal buses. However, most existing works consider only RC effects, e.g., the worst-case switching pattern resulting from coupling capacitance, to develop their encoding schemes to reduce bus delay. In this paper, we show that the worst-case switching patterns that incur the largest bus delay are completely different while considering RC and RLC effects. The finding implies that existing encoding schemes based on RC model might not improve or even worsen the bus delay when inductance effects become dominant.

Original languageEnglish
Pages (from-to)II945-II948
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 2004
Event2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada
Duration: 23 May 200426 May 2004


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