Rethinking Last-level-cache Write-back Strategy for MLC STT-RAM Main Memory with Asymmetric Write Energy

Yu Pei Liang, Tseng Yi Chen, Yuan Hao Chang, Shuo Han Chen, Pei Yu Chen, Wei Kuan Shih

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

To meet the requirement of low-power consumption, multi-level-cell STT-RAM (MLC STT-RAM) has been widely regarded as a potential candidate for replacing DRAM-based main memory in the next generation computer architectures because of its high memory cell density, fast read/write performance and zero refresh power consumption. However, MLC STT-RAM has higher power consumption than DRAM while a write operation is performed because MLC STT-RAM sometimes needs to perform a two-step transition to change the originally stored bits to another specifically written bit patterns. As a result, MLC STT-RAM has different power consumption while different bit patterns are written to a memory cell. To the best of our knowledge, a few or none of the previous studies rethink a cache replacement policy to overcome the asymmetric write energy issue of MLC STT-RAM-based main memory. Thus, this study proposes an energy-aware cache replacement policy, namely E-cache, which considers asymmetric write-back power consumption on MLC STT-RAM-based main memory to evict a proper cached data from the last-level cache, so as to minimize system power consumption. The experimental results show that the proposed solution reduces the energy consumption by 36% on average, compared with the LRU.

Original languageEnglish
Title of host publicationInternational Symposium on Low Power Electronics and Design, ISLPED 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728129549
DOIs
StatePublished - Jul 2019
Event2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019 - Lausanne, Switzerland
Duration: 29 Jul 201931 Jul 2019

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
Volume2019-July
ISSN (Print)1533-4678

Conference

Conference2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019
Country/TerritorySwitzerland
CityLausanne
Period29/07/1931/07/19

Keywords

  • asymmetric write energy
  • last-level cache management
  • replacement policy
  • STT-RAM

Fingerprint

Dive into the research topics of 'Rethinking Last-level-cache Write-back Strategy for MLC STT-RAM Main Memory with Asymmetric Write Energy'. Together they form a unique fingerprint.

Cite this