Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches

Yu Guang Chen; Ying Jing Tsai

doi:10.1109/DFT59622.2023.10313545

Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches

Yu Guang Chen, Ying Jing Tsai

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Computing-in-memory (CIM) has been considered as one of the promising solutions to overcome von Neumann bottleneck in the presence of data-intensive applications. Although various CIM architectures with CMOS-based and/or emerging memory devices have been proposed, the device and circuit non-idealities introduce reliability issues and cause inaccurate or even wrong computing results. In this tutorial, we attempt to introduce the source of unreliability, show the detection methods, and discuss reliability-aware CIM designs from both hardware and software perspectives for mitigating the reliability issues.

Original language	English
Title of host publication	36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023
Editors	Luca Cassano, Mihalis Psarakis, Marcello Traiola, Alberto Bosio
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350315004
DOIs	https://doi.org/10.1109/DFT59622.2023.10313545
State	Published - 2023
Event	36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023 - Juan-Les-Pins, France Duration: 3 Oct 2023 → 5 Oct 2023

Publication series

Name	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
ISSN (Print)	2576-1501
ISSN (Electronic)	2765-933X

Conference

Conference	36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023
Country/Territory	France
City	Juan-Les-Pins
Period	3/10/23 → 5/10/23

Keywords

Circuit Aging
Computing-in-memory
Reliability

Access to Document

10.1109/DFT59622.2023.10313545

運算記憶體之測試與可靠性增強技術-子計畫三：運算記憶體之老化偵測、緩解策略與自動化技術(3/3)
Chen, Y.-G. (PI)
1/08/25 → 31/07/26
Project: Research

Cite this

Chen, Y. G., & Tsai, Y. J. (2023). Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches. In L. Cassano, M. Psarakis, M. Traiola, & A. Bosio (Eds.), 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT59622.2023.10313545

Chen, Yu Guang ; Tsai, Ying Jing. / Reliability of Computing-In-Memories : Threats, Detection Methods, and Mitigation Approaches. 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. editor / Luca Cassano ; Mihalis Psarakis ; Marcello Traiola ; Alberto Bosio. Institute of Electrical and Electronics Engineers Inc., 2023. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT).

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abstract = "Computing-in-memory (CIM) has been considered as one of the promising solutions to overcome von Neumann bottleneck in the presence of data-intensive applications. Although various CIM architectures with CMOS-based and/or emerging memory devices have been proposed, the device and circuit non-idealities introduce reliability issues and cause inaccurate or even wrong computing results. In this tutorial, we attempt to introduce the source of unreliability, show the detection methods, and discuss reliability-aware CIM designs from both hardware and software perspectives for mitigating the reliability issues.",

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Chen, YG & Tsai, YJ 2023, Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches. in L Cassano, M Psarakis, M Traiola & A Bosio (eds), 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT, Institute of Electrical and Electronics Engineers Inc., 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023, Juan-Les-Pins, France, 3/10/23. https://doi.org/10.1109/DFT59622.2023.10313545

Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches. / Chen, Yu Guang; Tsai, Ying Jing.
36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. ed. / Luca Cassano; Mihalis Psarakis; Marcello Traiola; Alberto Bosio. Institute of Electrical and Electronics Engineers Inc., 2023. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - Computing-in-memory (CIM) has been considered as one of the promising solutions to overcome von Neumann bottleneck in the presence of data-intensive applications. Although various CIM architectures with CMOS-based and/or emerging memory devices have been proposed, the device and circuit non-idealities introduce reliability issues and cause inaccurate or even wrong computing results. In this tutorial, we attempt to introduce the source of unreliability, show the detection methods, and discuss reliability-aware CIM designs from both hardware and software perspectives for mitigating the reliability issues.

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Chen YG, Tsai YJ. Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches. In Cassano L, Psarakis M, Traiola M, Bosio A, editors, 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT). doi: 10.1109/DFT59622.2023.10313545

Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches

Abstract

Publication series

Conference

Keywords

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Projects

運算記憶體之測試與可靠性增強技術-子計畫三：運算記憶體之老化偵測、緩解策略與自動化技術(3/3)

Cite this