Abstract
This paper proposes a simple method for enhancing the reliability of static random access memories (SRAMs) with hard-to-detect resistive-open defects. The method prevents a SRAM from executing successive multiple read operations on the same position, such that the hard-to-detect defects cannot manifest as functional faults. This can prolong the lifetime of the SRAM with latent hard-to-detect defects. Experimental results show that the proposed reliability-enhancement circuit (REC) can effectively improve the reliability of the SRAMs without incurring delay penalty and with 0.07% additional area cost for an 8192 × 64-bit SRAM. By integrating the REC with the SRAM, a BISR scheme is proposed to boost 6%-10% increment of repair rate compared with the BISR without the REC. Also, the area cost of the BISR is lowonly about 2% for an 8192 × 64-bit SRAM.
Original language | English |
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Article number | 5210133 |
Pages (from-to) | 1361-1366 |
Number of pages | 6 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 18 |
Issue number | 9 |
DOIs | |
State | Published - Sep 2010 |
Keywords
- Random access memories
- built-in self-repair
- built-in self-test
- dynamic faults
- march test
- reliability
- static faults