Reconfigurable Hardware Accelerator of Morphological Image Processor

Ming Yi Lin, Sheng Hsien Hsieh, Ching Han Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Researchers emphasize the importance of hardware accelerators for mathematical morphology. If there are any issues, the hardware architecture may need to be redesigned. Thus, we propose a novel, reconfigurable hardware architecture with pipeline techniques for acceleration. With the order control register, there is no need to modify the architecture even if different results are expected. Furthermore, the hardware architecture caters to specific purposes instead of requiring a purpose-built hardware design.

Original languageEnglish
Title of host publication2023 IEEE 3rd International Conference on Electronic Communications, Internet of Things and Big Data, ICEIB 2023
EditorsTeen-Hang Meen
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages348-351
Number of pages4
ISBN (Electronic)9798350333862
DOIs
StatePublished - 2023
Event3rd IEEE International Conference on Electronic Communications, Internet of Things and Big Data, ICEIB 2023 - Taichung, Taiwan
Duration: 14 Apr 202316 Apr 2023

Publication series

Name2023 IEEE 3rd International Conference on Electronic Communications, Internet of Things and Big Data, ICEIB 2023

Conference

Conference3rd IEEE International Conference on Electronic Communications, Internet of Things and Big Data, ICEIB 2023
Country/TerritoryTaiwan
CityTaichung
Period14/04/2316/04/23

Keywords

  • grayscale image processing
  • hardware accelerator
  • pipeline
  • reconfigurable

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