TY - JOUR
T1 - ReBISR
T2 - A reconfigurable built-in self-repair scheme for random access memories in SOCs
AU - Tseng, Tsu Wei
AU - Li, Jin Fu
AU - Hsu, Chih Chiang
N1 - Funding Information:
Manuscript received September 14, 2008; revised January 01, 2009; accepted February 24, 2009. First published October 30, 2009; current version published May 26, 2010. A portion of this paper was published in the IEEE International Test Conference 2006. This work was supported in part by the National Science Council, Taiwan, under Contract NSC 97-2221-E-008-095-MY3 and by MOEA, Taiwan, under Contract 96-EC-17-A-01-S1-002. T.-W. Tseng and J.-F. Li are with the Department of Electrical Engineering, National Central University, Jhongli City 320, Taiwan. C.-C. Hsu is with Faraday Technology Cooperation, Hsinchu 300, Taiwan. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2009.2017906
PY - 2010/6
Y1 - 2010/6
N2 - Built-in self-repair (BISR) technique has been widely used to repair embedded random access memories (RAMs). This paper presents a reconfigurable BISR (ReBISR) scheme for repairing RAMs with different sizes and redundancy organizations. An efficient redundancy analysis algorithm is proposed to allocate redundancies of defective RAMs. In the ReBISR, a reconfigurable built-in redundancy analysis (ReBIRA) circuit is designed to perform the redundancy algorithm for various RAMs. Also, an adaptively reconfigurable fusing methodology is proposed to reduce the repair setup time when the RAMs are operated in normal mode. Experimental results show that the ReBISR scheme can achieve high repair rate (i.e., the ratio of the number of repaired RAMs to the number of defective RAMs). The area cost of the ReBISR is very small, which is only about 2.7% for four RAMs (one 4 Kbit RAM, one 16 Kbit RAM, one 128 Kbit RAM, and one 512 Kbit RAM). Moreover, the time overhead of redundancy analysis is very small. For example, the ratio of the redundancy analysis time to the test time for a 512 Kbit RAM tested by a March-14 N test with solid data backgrounds is only about 0.25%. On the other hand, the proposed fusing scheme can achieve about 86.94% reduction of repair setup time in comparison with a typical fusing scheme for 20 512× 16 × 64-bit RAMs of which each RAM has one spare row and one spare column.
AB - Built-in self-repair (BISR) technique has been widely used to repair embedded random access memories (RAMs). This paper presents a reconfigurable BISR (ReBISR) scheme for repairing RAMs with different sizes and redundancy organizations. An efficient redundancy analysis algorithm is proposed to allocate redundancies of defective RAMs. In the ReBISR, a reconfigurable built-in redundancy analysis (ReBIRA) circuit is designed to perform the redundancy algorithm for various RAMs. Also, an adaptively reconfigurable fusing methodology is proposed to reduce the repair setup time when the RAMs are operated in normal mode. Experimental results show that the ReBISR scheme can achieve high repair rate (i.e., the ratio of the number of repaired RAMs to the number of defective RAMs). The area cost of the ReBISR is very small, which is only about 2.7% for four RAMs (one 4 Kbit RAM, one 16 Kbit RAM, one 128 Kbit RAM, and one 512 Kbit RAM). Moreover, the time overhead of redundancy analysis is very small. For example, the ratio of the redundancy analysis time to the test time for a 512 Kbit RAM tested by a March-14 N test with solid data backgrounds is only about 0.25%. On the other hand, the proposed fusing scheme can achieve about 86.94% reduction of repair setup time in comparison with a typical fusing scheme for 20 512× 16 × 64-bit RAMs of which each RAM has one spare row and one spare column.
KW - Built-in redundancy analysis (BIRA)
KW - Built-in self-repair (BISR)
KW - Built-in self-test (BIST)
KW - March test
KW - Random access memory (RAM)
KW - Yield improvement
UR - http://www.scopus.com/inward/record.url?scp=77952951859&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2009.2017906
DO - 10.1109/TVLSI.2009.2017906
M3 - 期刊論文
AN - SCOPUS:77952951859
SN - 1063-8210
VL - 18
SP - 921
EP - 932
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 6
M1 - 5299100
ER -