Proportional static-phase-error reduction for frequency-multiplier-based delay-locked-loop architecture

Yo Hao Tu, Jen Chieh Liu, Kuo Hsing Cheng

Research output: Contribution to journalArticlepeer-review

Abstract

This paper proposes the proportional static-phase-error reduction (SPER) for the frequency-multiplier-based delay-locked-loop (DLL) architecture. The frequency multiplier (FM) can synthesize a combined clock to solve the high operational frequency of DLL. However, FM is sensitive to the static phase error of DLL. A SPER loop adopts a timing amplifier and a coarse-fine tuning technique to enhance the deterministic jitter of FM. The SPER loop proportionally reduces the static phase error and can extend the operating range of FM.

Original languageEnglish
Pages (from-to)655-658
Number of pages4
JournalIEICE Transactions on Electronics
VolumeE99C
Issue number6
DOIs
StatePublished - Jun 2016

Keywords

  • Delay-locked-loop
  • Edge-combiner
  • Frequency multiplier
  • Static-phase-error
  • Time amplifier

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