Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization

Kuo Hsing Cheng; Shun Wen Cheng

doi:10.1109/ASPDAC.2002.994909

Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization

Kuo Hsing Cheng, Shun Wen Cheng

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Comparing CMOS logic with pass-transistor logic, a question was raised in the minds of the authors: "does any rule exist that contains all good?" This paper reveals novel logic synthesis and optimization procedures for full swing arbitrary logic function. The novel procedures are called prioritized prime implicant patterns puzzle (PPIPP). Following the proposed procedures, we can get a new hybrid high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and is suitable for low supply voltage. It has full swing signal in all nodes and high robustness against transistor downsizing and voltage scaling.

Original language	English
Title of host publication	Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	155-159
Number of pages	5
ISBN (Electronic)	0769514413, 9780769514413
DOIs	https://doi.org/10.1109/ASPDAC.2002.994909
State	Published - 2002
Event	7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002 - Bangalore, India Duration: 7 Jan 2002 → 11 Jan 2002

Publication series

Name	Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Conference

Conference	7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
Country/Territory	India
City	Bangalore
Period	7/01/02 → 11/01/02

Keywords

full-swing logic
hybrid logic
Low power design
prime implicant
VLSI design

Access to Document

10.1109/ASPDAC.2002.994909

Cite this

Cheng, K. H., & Cheng, S. W. (2002). Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization. In Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002 (pp. 155-159). Article 994909 (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2002.994909

Cheng, Kuo Hsing ; Cheng, Shun Wen. / Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization. Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 155-159 (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002).

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abstract = "Comparing CMOS logic with pass-transistor logic, a question was raised in the minds of the authors: {"}does any rule exist that contains all good?{"} This paper reveals novel logic synthesis and optimization procedures for full swing arbitrary logic function. The novel procedures are called prioritized prime implicant patterns puzzle (PPIPP). Following the proposed procedures, we can get a new hybrid high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and is suitable for low supply voltage. It has full swing signal in all nodes and high robustness against transistor downsizing and voltage scaling.",

keywords = "full-swing logic, hybrid logic, Low power design, prime implicant, VLSI design",

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Cheng, KH & Cheng, SW 2002, Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization. in Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002., 994909, Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002, Institute of Electrical and Electronics Engineers Inc., pp. 155-159, 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002, Bangalore, India, 7/01/02. https://doi.org/10.1109/ASPDAC.2002.994909

Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization. / Cheng, Kuo Hsing; Cheng, Shun Wen.
Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., 2002. p. 155-159 994909 (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - Comparing CMOS logic with pass-transistor logic, a question was raised in the minds of the authors: "does any rule exist that contains all good?" This paper reveals novel logic synthesis and optimization procedures for full swing arbitrary logic function. The novel procedures are called prioritized prime implicant patterns puzzle (PPIPP). Following the proposed procedures, we can get a new hybrid high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and is suitable for low supply voltage. It has full swing signal in all nodes and high robustness against transistor downsizing and voltage scaling.

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Cheng KH, Cheng SW. Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization. In Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 155-159. 994909. (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002). doi: 10.1109/ASPDAC.2002.994909

Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization

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