Power driven two-level logic optimizer

Jyh Mou Tseng; Jing Yang Jou

Power driven two-level logic optimizer

Jyh Mou Tseng, Jing Yang Jou

Department of Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

5 Scopus citations

Abstract

In this paper we present Boolean techniques for reducing the power consumption in two-level combinational circuits. The two-level logic optimizer performs the logic minimization for low power targeting static PLA, general logic gates and dynamic PLA implementations. We modify Espresso algorithm by adding our heuristics that bias the logic minimization toward lowering the power dissipation. In our heuristics, signal probabilities and transition densities are two important parameters. The experimental results are promising.

Original language	English
Pages	113-116
Number of pages	4
State	Published - 1997
Event	Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC - Chiba, Jpn Duration: 28 Jan 1997 → 31 Jan 1997

Conference

Conference	Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC
City	Chiba, Jpn
Period	28/01/97 → 31/01/97

Cite this

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title = "Power driven two-level logic optimizer",

abstract = "In this paper we present Boolean techniques for reducing the power consumption in two-level combinational circuits. The two-level logic optimizer performs the logic minimization for low power targeting static PLA, general logic gates and dynamic PLA implementations. We modify Espresso algorithm by adding our heuristics that bias the logic minimization toward lowering the power dissipation. In our heuristics, signal probabilities and transition densities are two important parameters. The experimental results are promising.",

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AU - Tseng, Jyh Mou

AU - Jou, Jing Yang

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AB - In this paper we present Boolean techniques for reducing the power consumption in two-level combinational circuits. The two-level logic optimizer performs the logic minimization for low power targeting static PLA, general logic gates and dynamic PLA implementations. We modify Espresso algorithm by adding our heuristics that bias the logic minimization toward lowering the power dissipation. In our heuristics, signal probabilities and transition densities are two important parameters. The experimental results are promising.

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M3 - 會議論文

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T2 - Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC

Y2 - 28 January 1997 through 31 January 1997

ER -

Power driven two-level logic optimizer

Abstract

Conference

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Cite this