Post-linearization with image rejection for high IIP3 and image-rejection ratio of a 17 GHz CMOS low noise amplifier

Hwann Kaeo Chiou, Tsung Yu Yang

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

This study develops a post-linearization technique to simultaneously improve the input third-order intercept point (IIP3) and image-rejection ratio (IRR) of a 17 GHz low noise amplifier (LNA) in a 0.18 μm standard CMOS process. A third-order intermodulation distortion (IMD3) compensator constructed by a second-order notch filter was proposed to achieve both high linearity and image reject (IR) of the cascode LNA. The correlation between the post-linearization and IR techniques is analyzed and discussed. The measured LNA achieved a gain of 16.5 dB, a noise figure (NF) of 4.58 dB, an IIP3 of 0 dBm, and an IRR from 68 to 78 dB. The improvements of IIP3 and IRR are 11.7 and 46 dB, respectively, better than that of the LNA without the notch filter. The proposed IR LNA with total current dissipation of 4.8 mA under 1.8 V supply voltage and notch filter only dissipate a DC power of 2 mW.

Original languageEnglish
Pages (from-to)494-501
Number of pages8
JournalMicroelectronics Journal
Volume41
Issue number8
DOIs
StatePublished - Aug 2010

Keywords

  • CMOS
  • Image-rejection ratio
  • IMD3 compensator
  • Integrated active notch filter
  • Low noise amplifier
  • Post-linearization

Fingerprint

Dive into the research topics of 'Post-linearization with image rejection for high IIP3 and image-rejection ratio of a 17 GHz CMOS low noise amplifier'. Together they form a unique fingerprint.

Cite this