Post-bond test techniques for TSVs with crosstalk faults in 3D ICs

Yu Jen Huang, Jin Fu Li, Che Wei Chou

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

18 Scopus citations

Abstract

Three-dimensional (3D) integration is expected to cope with the difficulties faced by current 2D system-on-chip designs using through silicon via (TSV). However, coupling capacitance exists between two neighboring TSVs such that TSVs are prone to crosstalk faults. In this paper, we propose a builtin self-test (BIST) scheme for the post-bond test of TSVs with crosstalk faults in 3D ICs. A test algorithm for testing crosstalk faults of TSVs is proposed. The proposed BIST scheme has the feature of low area cost. Simulation results show that the area overhead of the BIST circuit implemented with 90nm CMOS technology for a 51216 TSV array in which each TSV cell size is 15 15m 2 is 6.7%.

Original languageEnglish
Title of host publication2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs
StatePublished - 2012
Event2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan
Duration: 23 Apr 201225 Apr 2012

Publication series

Name2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Conference

Conference2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
Country/TerritoryTaiwan
CityHsinchu
Period23/04/1225/04/12

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