Abstract
This paper proposes a method to select flip-flops for partial reset and/or partial scan for sequential circuits to increase their testability. The method gives weights for flip-flops for consideration for partial reset and/or scan based on information on required states for activating faults and the number of faults which propagate to flip-flops, which are obtained during test generation. Since the above information offers the reasons causing the untestable and/or hard-to-detect faults, the method is very efficient in locating flip-flops for partial reset and/or scan to ease test generation task. Experiments showed that this method selected less number of flip-flops for partial reset and scan while produced more testable circuits for benchmark circuits.
Original language | English |
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Pages | 341-346 |
Number of pages | 6 |
State | Published - 1998 |
Event | Proceedings of the 1998 16th IEEE VLSI Test Symposium - Monterey, CA, USA Duration: 26 Apr 1998 → 30 Apr 1998 |
Conference
Conference | Proceedings of the 1998 16th IEEE VLSI Test Symposium |
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City | Monterey, CA, USA |
Period | 26/04/98 → 30/04/98 |