Oscillation ring delay test for high performance microprocessors

Wen Ching Wu, Chung Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir

Research output: Contribution to journalArticlepeer-review

24 Scopus citations

Abstract

This paper proposes a new test scheme, oscillation ring test, and its associated test circuit organization for delay fault testing for high performance microprocessors. For this test scheme, the outputs of the circuit under test are connected to its inputs to form oscillation rings and test vectors which sensitize circuit paths are sought to make the rings oscillate. High speed transition counters or oscillation detectors can then be used to detect whether the circuit is working normally or not. The sensitizable paths of oscillation rings cover all circuit lines, detecting all gate delay faults, a large part of hazard free robust path delay faults and all the stuck-at faults. It has the advantage of testing the circuit at the working speed of the circuit. Also, with some modification, the scheme can also be used to measure the maximum speed of the circuit. The scheme needs minimal simple added hardware, thus ideal for testing, embedded circuits and microprocessors.

Original languageEnglish
Pages (from-to)147-155
Number of pages9
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Volume16
Issue number1-2
DOIs
StatePublished - 2000

Fingerprint

Dive into the research topics of 'Oscillation ring delay test for high performance microprocessors'. Together they form a unique fingerprint.

Cite this