When a multiple-output function (z1, z2,...,zm) of multilevel logic is realized by complex gates, the option often exists to realize either zi or its complement for each output. An efficient output phase assignment for the multilevel logic minimization (OPAM) is presented. The results of this study show that the proposed algorithm further reduces the literal count of the optimized network obtained by MIS (a multilevel logic minimization system).
|Number of pages||4|
|State||Published - 1989|
|Event||Proceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, USA|
Duration: 2 Oct 1989 → 4 Oct 1989
|Conference||Proceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors|
|City||Cambridge, MA, USA|
|Period||2/10/89 → 4/10/89|