OPAM: An efficient output phase assignment for multilevel logic minimization

Chin Long Wey; Sin Min Chang; Jing Yang Jou

OPAM: An efficient output phase assignment for multilevel logic minimization

Chin Long Wey, Sin Min Chang, Jing Yang Jou

Department of Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

When a multiple-output function (z₁, z₂,...,z_m) of multilevel logic is realized by complex gates, the option often exists to realize either z_i or its complement for each output. An efficient output phase assignment for the multilevel logic minimization (OPAM) is presented. The results of this study show that the proposed algorithm further reduces the literal count of the optimized network obtained by MIS (a multilevel logic minimization system).

Original language	English
Pages	270-273
Number of pages	4
State	Published - 1989
Event	Proceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, USA Duration: 2 Oct 1989 → 4 Oct 1989

Conference

Conference	Proceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors
City	Cambridge, MA, USA
Period	2/10/89 → 4/10/89

Cite this

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title = "OPAM: An efficient output phase assignment for multilevel logic minimization",

abstract = "When a multiple-output function (z1, z2,...,zm) of multilevel logic is realized by complex gates, the option often exists to realize either zi or its complement for each output. An efficient output phase assignment for the multilevel logic minimization (OPAM) is presented. The results of this study show that the proposed algorithm further reduces the literal count of the optimized network obtained by MIS (a multilevel logic minimization system).",

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year = "1989",

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T2 - Proceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors

AU - Wey, Chin Long

AU - Chang, Sin Min

AU - Jou, Jing Yang

PY - 1989

Y1 - 1989

N2 - When a multiple-output function (z1, z2,...,zm) of multilevel logic is realized by complex gates, the option often exists to realize either zi or its complement for each output. An efficient output phase assignment for the multilevel logic minimization (OPAM) is presented. The results of this study show that the proposed algorithm further reduces the literal count of the optimized network obtained by MIS (a multilevel logic minimization system).

AB - When a multiple-output function (z1, z2,...,zm) of multilevel logic is realized by complex gates, the option often exists to realize either zi or its complement for each output. An efficient output phase assignment for the multilevel logic minimization (OPAM) is presented. The results of this study show that the proposed algorithm further reduces the literal count of the optimized network obtained by MIS (a multilevel logic minimization system).

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M3 - 會議論文

AN - SCOPUS:0024902655

SP - 270

EP - 273

Y2 - 2 October 1989 through 4 October 1989

ER -

OPAM: An efficient output phase assignment for multilevel logic minimization

Abstract

Conference

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