@inproceedings{0041a47f33034aa5901b10b054272f3f,
title = "One-Transistor ferroelectric versatile memory: Strained-gate engineering for realizing energy-efficient switching and fast negative-capacitance operation",
abstract = "In this work, we report a ferroelectric versatile memory (FE-VM) with strained-gate engineering. The memory window of high strain case was improved by ∼47% at the same ferroelectric thickness, which agrees with the increase of orthorhombic crystallinity. Based on a reliable first principle calculation (FPC), we clarify that the gate strain accelerates the phase transformation from metastable monoclinic to orthorhombic and thus largely enhances the ferroelectric polarization without increasing dielectric thickness. On the other hand, the orthorhombic FE-AFE phase transition plays a key role in realizing negative capacitance (NC) effect at high gate electric field. This 1T strained-gate FE-VM with ferroelectric NC achieves a sub-60-mVdec subthreshold swing (SS) over ∼4 decade of ID to provide a 1∼10 fA/μm Ioff and >108 Ion/Ioff ratio, which allows for a fast 20-ns P/E switching during 1012 cycling endurance.",
author = "Chiu, {Yu Chien} and Cheng, {Chun Hu} and Chang, {Chun Yen} and Tang, {Ying Tsan} and Chen, {Min Cheng}",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 ; Conference date: 13-06-2016 Through 16-06-2016",
year = "2016",
month = sep,
day = "21",
doi = "10.1109/VLSIT.2016.7573414",
language = "???core.languages.en_GB???",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016",
}