On test and repair of 3D random access memory

Cheng Wen Wu; Shyue Kun Lu; Jin Fu Li

doi:10.1109/ASPDAC.2012.6165054

On test and repair of 3D random access memory

Cheng Wen Wu, Shyue Kun Lu, Jin Fu Li

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

13 Scopus citations

Abstract

The three-dimensional (3D) random access memory (RAM) using through-silicon via (TSV) has been considered as a promising approach to overcome the memory wall. However, cost and yield are two key issues for volume production of 3D RAMs, and yield enhancement increasingly requires test techniques. In this paper, we first introduce issues and existing techniques for the testing and yield enhancement of 3D RAMs. Then, a built-in self-repair (BISR) technique for 3D RAM using global redundancy is presented. According to the redundancy analysis results of each die with the BISR circuit, the die-to-die (d2d) and wafer-to-wafer (w2w) stacking problems are transferred to the bipartite maximal matching problem. Then, heuristic algorithms are also proposed to optimize the stacking yield.

Original language	English
Title of host publication	ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference
Pages	744-749
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2012.6165054
State	Published - 2012
Event	17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012 - Sydney, NSW, Australia Duration: 30 Jan 2012 → 2 Feb 2012

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012
Country/Territory	Australia
City	Sydney, NSW
Period	30/01/12 → 2/02/12

Access to Document

10.1109/ASPDAC.2012.6165054

Cite this

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title = "On test and repair of 3D random access memory",

abstract = "The three-dimensional (3D) random access memory (RAM) using through-silicon via (TSV) has been considered as a promising approach to overcome the memory wall. However, cost and yield are two key issues for volume production of 3D RAMs, and yield enhancement increasingly requires test techniques. In this paper, we first introduce issues and existing techniques for the testing and yield enhancement of 3D RAMs. Then, a built-in self-repair (BISR) technique for 3D RAM using global redundancy is presented. According to the redundancy analysis results of each die with the BISR circuit, the die-to-die (d2d) and wafer-to-wafer (w2w) stacking problems are transferred to the bipartite maximal matching problem. Then, heuristic algorithms are also proposed to optimize the stacking yield.",

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Wu, CW, Lu, SK & Li, JF 2012, On test and repair of 3D random access memory. in ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference., 6165054, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 744-749, 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, NSW, Australia, 30/01/12. https://doi.org/10.1109/ASPDAC.2012.6165054

On test and repair of 3D random access memory. / Wu, Cheng Wen; Lu, Shyue Kun; Li, Jin Fu.

ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. 2012. p. 744-749 6165054 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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On test and repair of 3D random access memory

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