On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model

Chun Yao Wang, Shing Wu Tung, Jing Yang Jou

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Embedded cores are being increasingly used in the design of large System-on-a-Chip. Because of the high complexity of SoC, the design verification is a challenge for system integrator To reduce the verification complexity, the port order fault model proposed by Tung and Jou (1998) has been used for verifying core-based designs and the corresponding verification pattern generation have been developed. Adders and multipliers are the most often used data path elements in core-based designs. Due to their regularity, the development of the verification pattern sets can be achieved in a systematic method. In this paper, we present the algorithms of generating the minimum verification pattern sets for adders and multipliers and these pattern sets are much smaller than that obtained from the automatic verification pattern generation proposed by Wang, Tung and Jou (2001).

Original languageEnglish
Title of host publicationProceedings - 6th IEEE International High-Level Design Validation and Test Workshop, HLDVT 2002
PublisherIEEE Computer Society
Pages145-150
Number of pages6
ISBN (Electronic)0769514111
DOIs
StatePublished - 2001
Event6th IEEE International High-Level Design Validation and Test Workshop, HLDVT 2002 - Monterey, United States
Duration: 7 Nov 20019 Nov 2001

Publication series

NameProceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT
Volume2001-January
ISSN (Print)1552-6674

Conference

Conference6th IEEE International High-Level Design Validation and Test Workshop, HLDVT 2002
Country/TerritoryUnited States
CityMonterey
Period7/11/019/11/01

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