On automatic-verification pattern generation for SoC with port-order fault model

Chun Yao Wang, Shing Wu Tung, Jing Yang Jou

Research output: Contribution to journalArticlepeer-review

17 Scopus citations

Abstract

Embedded cores are being increasingly used in the designs of large system-on-a-chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrators. To reduce the verification complexity, the port-order fault (POF) model has been used for verifying core-based designs (Tung and Jou, 1998). In this paper, we present an automatic-verification pattern generation (AVPG) for SoC design verification based on the POF model and perform experiments on combinational and sequential benchmarks. Experimental results show that our AVPG can efficiently generate verification patterns with high POF coverage.

Original languageEnglish
Pages (from-to)466-479
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume21
Issue number4
DOIs
StatePublished - Apr 2002

Keywords

  • Automatic-verification pattern generation (AVPG)
  • Design verification
  • IEEE P1500
  • Port-order fault (POF)
  • SoC
  • Undetected port sequence (UPS)

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