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A novel concept of NVDimm-FE has been proposed to replace the DRAM position in the memory hierarchy. A high-density 3D architecture of 3-bit-per-CFE 2-transistors and n-ferroelectric-capacitances (3-bit/c 2TnCFE) array has been developed as a platform to realize this concept. Our results have shown that 3D 3-bit/c 2TnCFE array achieves 3.1V of the memory window, 62% of the program (PGM) efficiency, 10 ns of PGM-speed at 2.1MV/cm, excellent endurance up to 1010 times for each state of 3-bits per CFE (8 states), and retention for decade-lifetime prediction of the ferroelectric-NVMs at 103 °C. With the assistance of 3D integration of many vertical CFE layers, the 2TnCFE has been proved to be an ultra-high-density candidate of the NVDimm-FE to break the GREAT memory wall and boost high-performance computing efficiency in the future.
|Title of host publication||2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|State||Published - 2022|
|Event||2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States|
Duration: 12 Jun 2022 → 17 Jun 2022
|Name||Digest of Technical Papers - Symposium on VLSI Technology|
|Conference||2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022|
|Period||12/06/22 → 17/06/22|
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