NVDimm-FE: A High-density 3D Architecture of 3-bit/c 2TnCFEto Break Great Memory Wall with 10 ns of PGM-pulse, 1010Cycles of Endurance, and Decade Lifetime at 103 °C

E. R. Hsieh; J. K. Chang; T. Y. Tang; Y. J. Li; C. W. Liang; M. Y. Lin; S. Y. Huang; C. J. Su; J. C. Guo; S. S. Chung

doi:10.1109/VLSITechnologyandCir46769.2022.9830515

NVDimm-FE: A High-density 3D Architecture of 3-bit/c 2TnC_FEto Break Great Memory Wall with 10 ns of PGM-pulse, 10¹⁰Cycles of Endurance, and Decade Lifetime at 103 °C

E. R. Hsieh, J. K. Chang, T. Y. Tang, Y. J. Li, C. W. Liang, M. Y. Lin, S. Y. Huang, C. J. Su, J. C. Guo, S. S. Chung

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

A novel concept of NVDimm-FE has been proposed to replace the DRAM position in the memory hierarchy. A high-density 3D architecture of 3-bit-per-CFE 2-transistors and n-ferroelectric-capacitances (3-bit/c 2TnCFE) array has been developed as a platform to realize this concept. Our results have shown that 3D 3-bit/c 2TnCFE array achieves 3.1V of the memory window, 62% of the program (PGM) efficiency, 10 ns of PGM-speed at 2.1MV/cm, excellent endurance up to 1010 times for each state of 3-bits per CFE (8 states), and retention for decade-lifetime prediction of the ferroelectric-NVMs at 103 °C. With the assistance of 3D integration of many vertical CFE layers, the 2TnCFE has been proved to be an ultra-high-density candidate of the NVDimm-FE to break the GREAT memory wall and boost high-performance computing efficiency in the future.

Original language	English
Title of host publication	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	359-360
Number of pages	2
ISBN (Electronic)	9781665497725
DOIs	https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830515
State	Published - 2022
Event	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States Duration: 12 Jun 2022 → 17 Jun 2022

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2022-June
ISSN (Print)	0743-1562

Conference

Conference	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Country/Territory	United States
City	Honolulu
Period	12/06/22 → 17/06/22

Access to Document

10.1109/VLSITechnologyandCir46769.2022.9830515

Developments and Applications of AI chip by Neuromorphic Computing: Construction of General Neuron-Network Technology Platform and Hetero-Integration of AI Chip in Recognition of Images(1/3)
Hsieh, E.-R. (PI)
1/02/20 → 31/01/21
Project: Research

Cite this

Hsieh, E. R., Chang, J. K., Tang, T. Y., Li, Y. J., Liang, C. W., Lin, M. Y., Huang, S. Y., Su, C. J., Guo, J. C., & Chung, S. S. (2022). NVDimm-FE: A High-density 3D Architecture of 3-bit/c 2TnC_FEto Break Great Memory Wall with 10 ns of PGM-pulse, 10¹⁰Cycles of Endurance, and Decade Lifetime at 103 °C. In 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 (pp. 359-360). (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830515

Hsieh, E. R. ; Chang, J. K. ; Tang, T. Y. et al. / NVDimm-FE : A High-density 3D Architecture of 3-bit/c 2TnC_FEto Break Great Memory Wall with 10 ns of PGM-pulse, 10¹⁰Cycles of Endurance, and Decade Lifetime at 103 °C. 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc., 2022. pp. 359-360 (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{603bcf10f191450dbed2738c18124394,

title = "NVDimm-FE: A High-density 3D Architecture of 3-bit/c 2TnCFEto Break Great Memory Wall with 10 ns of PGM-pulse, 1010Cycles of Endurance, and Decade Lifetime at 103 °C",

abstract = "A novel concept of NVDimm-FE has been proposed to replace the DRAM position in the memory hierarchy. A high-density 3D architecture of 3-bit-per-CFE 2-transistors and n-ferroelectric-capacitances (3-bit/c 2TnCFE) array has been developed as a platform to realize this concept. Our results have shown that 3D 3-bit/c 2TnCFE array achieves 3.1V of the memory window, 62% of the program (PGM) efficiency, 10 ns of PGM-speed at 2.1MV/cm, excellent endurance up to 1010 times for each state of 3-bits per CFE (8 states), and retention for decade-lifetime prediction of the ferroelectric-NVMs at 103 °C. With the assistance of 3D integration of many vertical CFE layers, the 2TnCFE has been proved to be an ultra-high-density candidate of the NVDimm-FE to break the GREAT memory wall and boost high-performance computing efficiency in the future.",

author = "Hsieh, {E. R.} and Chang, {J. K.} and Tang, {T. Y.} and Li, {Y. J.} and Liang, {C. W.} and Lin, {M. Y.} and Huang, {S. Y.} and Su, {C. J.} and Guo, {J. C.} and Chung, {S. S.}",

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Hsieh, ER, Chang, JK, Tang, TY, Li, YJ, Liang, CW, Lin, MY, Huang, SY, Su, CJ, Guo, JC & Chung, SS 2022, NVDimm-FE: A High-density 3D Architecture of 3-bit/c 2TnC_FEto Break Great Memory Wall with 10 ns of PGM-pulse, 10¹⁰Cycles of Endurance, and Decade Lifetime at 103 °C. in 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2022-June, Institute of Electrical and Electronics Engineers Inc., pp. 359-360, 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022, Honolulu, United States, 12/06/22. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830515

NVDimm-FE: A High-density 3D Architecture of 3-bit/c 2TnC_FEto Break Great Memory Wall with 10 ns of PGM-pulse, 10¹⁰Cycles of Endurance, and Decade Lifetime at 103 °C. / Hsieh, E. R.; Chang, J. K.; Tang, T. Y. et al.
2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 359-360 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - A novel concept of NVDimm-FE has been proposed to replace the DRAM position in the memory hierarchy. A high-density 3D architecture of 3-bit-per-CFE 2-transistors and n-ferroelectric-capacitances (3-bit/c 2TnCFE) array has been developed as a platform to realize this concept. Our results have shown that 3D 3-bit/c 2TnCFE array achieves 3.1V of the memory window, 62% of the program (PGM) efficiency, 10 ns of PGM-speed at 2.1MV/cm, excellent endurance up to 1010 times for each state of 3-bits per CFE (8 states), and retention for decade-lifetime prediction of the ferroelectric-NVMs at 103 °C. With the assistance of 3D integration of many vertical CFE layers, the 2TnCFE has been proved to be an ultra-high-density candidate of the NVDimm-FE to break the GREAT memory wall and boost high-performance computing efficiency in the future.

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Hsieh ER, Chang JK, Tang TY, Li YJ, Liang CW, Lin MY et al. NVDimm-FE: A High-density 3D Architecture of 3-bit/c 2TnC_FEto Break Great Memory Wall with 10 ns of PGM-pulse, 10¹⁰Cycles of Endurance, and Decade Lifetime at 103 °C. In 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 359-360. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSITechnologyandCir46769.2022.9830515