NVDimm-FE: A High-density 3D Architecture of 3-bit/c 2TnCFEto Break Great Memory Wall with 10 ns of PGM-pulse, 1010Cycles of Endurance, and Decade Lifetime at 103 °C

E. R. Hsieh, J. K. Chang, T. Y. Tang, Y. J. Li, C. W. Liang, M. Y. Lin, S. Y. Huang, C. J. Su, J. C. Guo, S. S. Chung

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

A novel concept of NVDimm-FE has been proposed to replace the DRAM position in the memory hierarchy. A high-density 3D architecture of 3-bit-per-CFE 2-transistors and n-ferroelectric-capacitances (3-bit/c 2TnCFE) array has been developed as a platform to realize this concept. Our results have shown that 3D 3-bit/c 2TnCFE array achieves 3.1V of the memory window, 62% of the program (PGM) efficiency, 10 ns of PGM-speed at 2.1MV/cm, excellent endurance up to 1010 times for each state of 3-bits per CFE (8 states), and retention for decade-lifetime prediction of the ferroelectric-NVMs at 103 °C. With the assistance of 3D integration of many vertical CFE layers, the 2TnCFE has been proved to be an ultra-high-density candidate of the NVDimm-FE to break the GREAT memory wall and boost high-performance computing efficiency in the future.

Original languageEnglish
Title of host publication2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages359-360
Number of pages2
ISBN (Electronic)9781665497725
DOIs
StatePublished - 2022
Event2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States
Duration: 12 Jun 202217 Jun 2022

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2022-June
ISSN (Print)0743-1562

Conference

Conference2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Country/TerritoryUnited States
CityHonolulu
Period12/06/2217/06/22

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