Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints

Yu Guang Chen, Wan Yu Wen, Yiyu Shi, Wing Kai Hon, Shih Chieh Chang

Research output: Contribution to journalArticlepeer-review

20 Scopus citations


In 3-D integrated circuits, through silicon via (TSV) is a critical enabling technique to provide vertical connections. However, it may suffer from many reliability issues such as undercut, misalignment, or random open defects. Various fault-tolerance mechanisms have been proposed in literature to improve yield, at the cost of significant area overhead. In this paper, we focus on the structure that uses one spare TSV for a group of original TSVs, and study the optimal assignment of spare TSVs under yield and timing constraints to minimize the total area overhead. We show that such problem can be modeled as a constrained graph decomposition problem. Two efficient heuristics are further developed to address this problem. Experimental results show that under the same yield and timing constraints, our heuristic can reduce the area overhead induced by the fault-tolerance mechanisms by up to 61%, compared with a seemingly more intuitive nearest-neighbor-based heuristic.

Original languageEnglish
Article number6998006
Pages (from-to)577-588
Number of pages12
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number4
StatePublished - 1 Apr 2015


  • Fault-tolerance
  • reliability
  • three dimensional integrated circuits (3-D IC)
  • through silicon via (TSV)


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