Warpage has become a very critical reliability problem for the advanced electronic packaging technique. One or more chips are stacked on the substrates for a device. The device thus contains materials that have different physical properties. The most prominent problem would be the differences in the thermal expansion coefficient for these materials. During fabrication, thermal energy was applied to the chips; the expansion of these materials would induce thermal stress and warpage on the chips that would be harmful to the long-term reliability. When a current is applied to the device, the Joule heating may further enhance the warpage of the chips. Si-on-Si interposer samples are introduced to minimize the issue. It is important to develop a quick and non-destructive method to insitu analyze the warpage level at different conditions. Synchrotron radiation X-ray is used for measuring the strain and the warpage of the Si dies.