Noise-constrained performance optimization by simultaneous gate and wire sizing based on Lagrangian relaxation

Hui Ru Jiang, Jing Yang Jou, Yao Wen Chang

Research output: Contribution to journalConference articlepeer-review

8 Scopus citations

Abstract

Noise, as well as area, delay, and power, is one of the most important concerns in the design of deep sub-micron ICs. Currently existing algorithms can not handle simultaneous switching conditions of signals for noise minimization. In this paper, we model not only physical coupling capacitance, but also simultaneous switching behavior for noise optimization. Based on Lagrangian relaxation, we present an algorithm that can optimally solve the simultaneous noise, area, delay, and power optimization problem by sizing circuit components. Our algorithm, with linear memory requirement overall and linear runtime per iteration, is very effective and efficient. For example, for a circuit of 6144 wires and 3512 gates, our algorithm solves the simultaneous optimization problem using only 2.1 MB memory and 47 minute runtime to achieve the precision of within 1% error on a SUN UltraSPARC-I workstation.

Original languageEnglish
Pages (from-to)90-95
Number of pages6
JournalProceedings - Design Automation Conference
DOIs
StatePublished - 1999
EventProceedings of the 1999 36th Annual Design Automation Conference (DAC) - New Orleans, LA, USA
Duration: 21 Jun 199925 Jun 1999

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