TY - JOUR

T1 - My-box representation for faulty CMOS circuits

AU - Chen, J. E.

AU - Lee, C. L.

AU - Shen, W. Z.

PY - 1990

Y1 - 1990

N2 - A new logic element, My-box, is proposed to model the line faults (stuck-at-1 and stuck-at-0) and the transistor faults (stuck-on and stuck-open) of CMOS circuits, which consist of fully CMOS logic, pseudo nMOS logic, dynamic CMOS logic, clocked CMOS (C2MOS) logic, CMOS domino logic and NORA CMOS logic. It can also be used to model the faults and the functions of a transmission gate logic. A procedure is described to transform a transistor level CMOS circuit to a gate-level equivalent circuit which is composed of AND, OR and the My-box logic element. A fault collapsing procedure is also derived to determine the representative set of prime faults (RSPF) for the transformed gate-level circuit. By applying this procedure to ten benchmark circuits, the number of faults can be reduced to approximately 15% of the original total faults, if the ten benchmark circuits are implemented in the fully CMOS logic.

AB - A new logic element, My-box, is proposed to model the line faults (stuck-at-1 and stuck-at-0) and the transistor faults (stuck-on and stuck-open) of CMOS circuits, which consist of fully CMOS logic, pseudo nMOS logic, dynamic CMOS logic, clocked CMOS (C2MOS) logic, CMOS domino logic and NORA CMOS logic. It can also be used to model the faults and the functions of a transmission gate logic. A procedure is described to transform a transistor level CMOS circuit to a gate-level equivalent circuit which is composed of AND, OR and the My-box logic element. A fault collapsing procedure is also derived to determine the representative set of prime faults (RSPF) for the transformed gate-level circuit. By applying this procedure to ten benchmark circuits, the number of faults can be reduced to approximately 15% of the original total faults, if the ten benchmark circuits are implemented in the fully CMOS logic.

UR - http://www.scopus.com/inward/record.url?scp=0025436849&partnerID=8YFLogxK

U2 - 10.1049/ip-g-2.1990.0034

DO - 10.1049/ip-g-2.1990.0034

M3 - 期刊論文

AN - SCOPUS:0025436849

VL - 137

SP - 225

EP - 232

JO - IEE proceedings. Part G. Electronic circuits and systems

JF - IEE proceedings. Part G. Electronic circuits and systems

SN - 0143-7089

IS - 3

ER -