Skip to main navigation
Skip to search
Skip to main content
National Central University Home
Help & FAQ
English
中文
Home
Scholar Profiles
Research units
Projects
Research output
Datasets
Prizes
Activities
Press/Media
Impacts
Search by expertise, name or affiliation
Multilevel full-chip routing with testability and yield enhancement
Katherine Shu Min Li
, Chung Len Lee
, Yao Wen Chang
, Chauchin Su
, Jwu E. Chen
Department of Electrical Engineering
Research output
:
Contribution to journal
›
Conference article
›
peer-review
2
Scopus citations
Overview
Fingerprint
Fingerprint
Dive into the research topics of 'Multilevel full-chip routing with testability and yield enhancement'. Together they form a unique fingerprint.
Sort by
Weight
Alphabetically
Keyphrases
Benchmark Circuits
33%
Congestion
100%
Crosstalk Effect
33%
Diagnosability
33%
Diagnosis Scheme
33%
Fault Coverage
33%
Fault Probability
33%
Full-chip
100%
Manufacturability
66%
Multiple Faults
33%
Optical Proximity Correction
33%
Oscillation Ring
66%
Ring Method
33%
Ring Test
33%
Router
33%
Routing Algorithm
66%
Routing Congestion
33%
Routing Density
33%
Routing Framework
33%
Signal Integrity
33%
Testability
100%
Yield Improvement
100%
Computer Science
Benchmark Circuit
50%
Experimental Result
100%
Fault Coverage
50%
Routing Algorithm
100%
Routing Congestion
50%
Routing Density
50%
Signal Integrity
50%
Yield Enhancement
100%
Engineering
Crosstalk
33%
Experimental Result
66%
Interconnects
66%
Manufacturability
66%
Routing Algorithm
66%
Testability
100%