More strain and less stress- The guideline for developing high-end strained CMOS technologie s with acceptable reliability

Steve S. Chung; E. R. Hsieh; D. C. Huang; C. S. Lai; C. H. Tsai; P. W. Liu; Y. H. Lin; C. T. Tsai; G. H. Ma; S. C. Chien; S. W. Sun

doi:10.1109/IEDM.2008.4796718

More strain and less stress- The guideline for developing high-end strained CMOS technologie s with acceptable reliability

Steve S. Chung, E. R. Hsieh, D. C. Huang, C. S. Lai, C. H. Tsai, P. W. Liu, Y. H. Lin, C. T. Tsai, G. H. Ma, S. C. Chien, S. W. Sun

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

In this paper, the design guideline with emphasis on CMOS device reliability has been addressed. Advanced 65nm CMOS devices with various strain engineering were evaluated. For nMOSFETs, charge pumping(CP) measurement is efficient for their reliability characterizations. Although biaxial strained SiGe-channel device provides good driving current enhancement, it suffers from the Ge out-diffusion such that exhibits worse reliability. The SSOI device exhibits good hot-carrier immunity, but its interface quality needs special care during the process. In addition, SiC on S/D device is an alternative for high current enhancement, but its off-state junction leakage is serious. Then, CESL device becomes the most promising technology with high performance and the best reliability, especially with process simplicity. For pMOSFETs, both uniaxial and biaxial strained devices have been studied. For the first time, an accurate representation of interface trap(Nit) profiling, suitable for HC and NBTI analyses, has been developed by an improved DCIV method. The uniaxial- strained device shows much better reliability, in particular a special class of SiGe S/D device with EDB design seems to be promising. These results provide a valuable guideline for the aggressive design of strained CMOS technologies.

Original language	English
Title of host publication	2008 IEEE International Electron Devices Meeting, IEDM 2008
DOIs	https://doi.org/10.1109/IEDM.2008.4796718
State	Published - 2008
Event	2008 IEEE International Electron Devices Meeting, IEDM 2008 - San Francisco, CA, United States Duration: 15 Dec 2008 → 17 Dec 2008

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Conference

Conference	2008 IEEE International Electron Devices Meeting, IEDM 2008
Country/Territory	United States
City	San Francisco, CA
Period	15/12/08 → 17/12/08

Access to Document

10.1109/IEDM.2008.4796718

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Chung, S. S., Hsieh, E. R., Huang, D. C., Lai, C. S., Tsai, C. H., Liu, P. W., Lin, Y. H., Tsai, C. T., Ma, G. H., Chien, S. C., & Sun, S. W. (2008). More strain and less stress- The guideline for developing high-end strained CMOS technologie s with acceptable reliability. In 2008 IEEE International Electron Devices Meeting, IEDM 2008 Article 4796718 (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2008.4796718

@inproceedings{7c3c61a8053b434c93ee361f7b5cb6d6,

title = "More strain and less stress- The guideline for developing high-end strained CMOS technologie s with acceptable reliability",

abstract = "In this paper, the design guideline with emphasis on CMOS device reliability has been addressed. Advanced 65nm CMOS devices with various strain engineering were evaluated. For nMOSFETs, charge pumping(CP) measurement is efficient for their reliability characterizations. Although biaxial strained SiGe-channel device provides good driving current enhancement, it suffers from the Ge out-diffusion such that exhibits worse reliability. The SSOI device exhibits good hot-carrier immunity, but its interface quality needs special care during the process. In addition, SiC on S/D device is an alternative for high current enhancement, but its off-state junction leakage is serious. Then, CESL device becomes the most promising technology with high performance and the best reliability, especially with process simplicity. For pMOSFETs, both uniaxial and biaxial strained devices have been studied. For the first time, an accurate representation of interface trap(Nit) profiling, suitable for HC and NBTI analyses, has been developed by an improved DCIV method. The uniaxial- strained device shows much better reliability, in particular a special class of SiGe S/D device with EDB design seems to be promising. These results provide a valuable guideline for the aggressive design of strained CMOS technologies.",

author = "Chung, {Steve S.} and Hsieh, {E. R.} and Huang, {D. C.} and Lai, {C. S.} and Tsai, {C. H.} and Liu, {P. W.} and Lin, {Y. H.} and Tsai, {C. T.} and Ma, {G. H.} and Chien, {S. C.} and Sun, {S. W.}",

year = "2008",

doi = "10.1109/IEDM.2008.4796718",

language = "???core.languages.en_GB???",

isbn = "9781424423781",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

booktitle = "2008 IEEE International Electron Devices Meeting, IEDM 2008",

note = "2008 IEEE International Electron Devices Meeting, IEDM 2008 ; Conference date: 15-12-2008 Through 17-12-2008",

}

Chung, SS, Hsieh, ER, Huang, DC, Lai, CS, Tsai, CH, Liu, PW, Lin, YH, Tsai, CT, Ma, GH, Chien, SC & Sun, SW 2008, More strain and less stress- The guideline for developing high-end strained CMOS technologie s with acceptable reliability. in 2008 IEEE International Electron Devices Meeting, IEDM 2008., 4796718, Technical Digest - International Electron Devices Meeting, IEDM, 2008 IEEE International Electron Devices Meeting, IEDM 2008, San Francisco, CA, United States, 15/12/08. https://doi.org/10.1109/IEDM.2008.4796718

More strain and less stress- The guideline for developing high-end strained CMOS technologie s with acceptable reliability. / Chung, Steve S.; Hsieh, E. R.; Huang, D. C. et al.
2008 IEEE International Electron Devices Meeting, IEDM 2008. 2008. 4796718 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - More strain and less stress- The guideline for developing high-end strained CMOS technologie s with acceptable reliability

AU - Chung, Steve S.

AU - Hsieh, E. R.

AU - Huang, D. C.

AU - Lai, C. S.

AU - Tsai, C. H.

AU - Liu, P. W.

AU - Lin, Y. H.

AU - Tsai, C. T.

AU - Ma, G. H.

AU - Chien, S. C.

AU - Sun, S. W.

PY - 2008

Y1 - 2008

N2 - In this paper, the design guideline with emphasis on CMOS device reliability has been addressed. Advanced 65nm CMOS devices with various strain engineering were evaluated. For nMOSFETs, charge pumping(CP) measurement is efficient for their reliability characterizations. Although biaxial strained SiGe-channel device provides good driving current enhancement, it suffers from the Ge out-diffusion such that exhibits worse reliability. The SSOI device exhibits good hot-carrier immunity, but its interface quality needs special care during the process. In addition, SiC on S/D device is an alternative for high current enhancement, but its off-state junction leakage is serious. Then, CESL device becomes the most promising technology with high performance and the best reliability, especially with process simplicity. For pMOSFETs, both uniaxial and biaxial strained devices have been studied. For the first time, an accurate representation of interface trap(Nit) profiling, suitable for HC and NBTI analyses, has been developed by an improved DCIV method. The uniaxial- strained device shows much better reliability, in particular a special class of SiGe S/D device with EDB design seems to be promising. These results provide a valuable guideline for the aggressive design of strained CMOS technologies.

AB - In this paper, the design guideline with emphasis on CMOS device reliability has been addressed. Advanced 65nm CMOS devices with various strain engineering were evaluated. For nMOSFETs, charge pumping(CP) measurement is efficient for their reliability characterizations. Although biaxial strained SiGe-channel device provides good driving current enhancement, it suffers from the Ge out-diffusion such that exhibits worse reliability. The SSOI device exhibits good hot-carrier immunity, but its interface quality needs special care during the process. In addition, SiC on S/D device is an alternative for high current enhancement, but its off-state junction leakage is serious. Then, CESL device becomes the most promising technology with high performance and the best reliability, especially with process simplicity. For pMOSFETs, both uniaxial and biaxial strained devices have been studied. For the first time, an accurate representation of interface trap(Nit) profiling, suitable for HC and NBTI analyses, has been developed by an improved DCIV method. The uniaxial- strained device shows much better reliability, in particular a special class of SiGe S/D device with EDB design seems to be promising. These results provide a valuable guideline for the aggressive design of strained CMOS technologies.

UR - http://www.scopus.com/inward/record.url?scp=64549107997&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2008.4796718

DO - 10.1109/IEDM.2008.4796718

M3 - 會議論文篇章

AN - SCOPUS:64549107997

SN - 9781424423781

T3 - Technical Digest - International Electron Devices Meeting, IEDM

BT - 2008 IEEE International Electron Devices Meeting, IEDM 2008

T2 - 2008 IEEE International Electron Devices Meeting, IEDM 2008

Y2 - 15 December 2008 through 17 December 2008

ER -

More strain and less stress- The guideline for developing high-end strained CMOS technologie s with acceptable reliability

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