Methodology for fault model development for hierarchical linear systems

Yin Chao Huang, Chung Len Lee, Jun Weir Lin, Jwu E. Chen, Chau chin Su

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations


In this paper, a methodology to develop fault models for hierarchical linear systems which are composed of operational amplifiers (OP) is demonstrated and presented. The methodology, at first, presents a transfer function model for the open-loop OP based on analysis of element faults at the transistor level. Then it derives a transfer function model for the closed loop OP based on the derived open-loop OP level model, again a higher level fault model for a module which is composed of closed loop OPs. The models can handle ac faults. The benchmark state-variable filter is used as an example to demonstrate for this methodology. An application of the derived models to Monte-Carlo simulation to save computation time is also demonstrated.

Original languageEnglish
Pages (from-to)90-95
Number of pages6
JournalProceedings of the Asian Test Symposium
StatePublished - 2000
Event9th Asian Test Symposium - Taipei, Taiwan
Duration: 4 Dec 20006 Dec 2000


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