This paper proposes a 3 GHz built-in jitter measurement (BIJM) circuit to measure clock jitter on high-speed transceivers and SoC systems. The proposed BIJM circuit adopts a high timing resolution and self-calibration techniques and discusses the measurement error issues. The measurement error source is analyzed each block in BIJM. To eliminate process variation effects in 3 GHz systems, this study proposes an auto-calibration technique for the self-refereed circuit and other calibration techniques for the time amplifier (TA) and vernier ring oscillator (VRO). Because the vernier ring oscillator and time amplifier achieve a small timing resolution, the BIJM circuit does not need an additional jitter-free reference signal using the self-refereed circuit. This study fabricated the BIJM circuit using the UMC 90 nm CMOS process. The BIJM circuit measured the Gaussian distribution jitter at a 1.8 ps timing resolution with a 3 GHz input clock frequency.