Low voltage low power high-speed BiCMOS multiplier

Kuo Hsing Cheng; Yu Kwang Yeha; Farn Son Lian

Low voltage low power high-speed BiCMOS multiplier

Kuo Hsing Cheng, Yu Kwang Yeha, Farn Son Lian

Department of Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

A 16×16-bit parallel multiplier fabricated in a 1.0-μm BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth's algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 μW at 2.5 V supply voltage operation.

Original language	English
Pages	p 4
State	Published - 1998
Event	Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology - Lisboa, Portugal Duration: 7 Sep 1998 → 10 Sep 1998

Conference

Conference	Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology
City	Lisboa, Portugal
Period	7/09/98 → 10/09/98

Cite this

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title = "Low voltage low power high-speed BiCMOS multiplier",

abstract = "A 16×16-bit parallel multiplier fabricated in a 1.0-μm BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth's algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 μW at 2.5 V supply voltage operation.",

author = "Cheng, {Kuo Hsing} and Yeha, {Yu Kwang} and Lian, {Farn Son}",

year = "1998",

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pages = "p 4",

note = "Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology ; Conference date: 07-09-1998 Through 10-09-1998",

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Low voltage low power high-speed BiCMOS multiplier. / Cheng, Kuo Hsing; Yeha, Yu Kwang; Lian, Farn Son.
1998. p 4 Paper presented at Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology, Lisboa, Portugal.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - Low voltage low power high-speed BiCMOS multiplier

AU - Cheng, Kuo Hsing

AU - Yeha, Yu Kwang

AU - Lian, Farn Son

PY - 1998

Y1 - 1998

N2 - A 16×16-bit parallel multiplier fabricated in a 1.0-μm BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth's algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 μW at 2.5 V supply voltage operation.

AB - A 16×16-bit parallel multiplier fabricated in a 1.0-μm BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth's algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 μW at 2.5 V supply voltage operation.

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M3 - 會議論文

AN - SCOPUS:0032265326

SP - p 4

T2 - Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology

Y2 - 7 September 1998 through 10 September 1998

ER -

Low voltage low power high-speed BiCMOS multiplier

Abstract

Conference

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