Low voltage low power high-speed BiCMOS multiplier

Kuo Hsing Cheng; Yu Kwang Yeha; Farn Sou Lian

doi:10.1109/ICECS.1998.814820

Low voltage low power high-speed BiCMOS multiplier

Kuo Hsing Cheng, Yu Kwang Yeha, Farn Sou Lian

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

A 16×16-bit parallel multiplier fabricated in a 1.0 μm BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth's algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 μW at 2.5 V supply voltage operation.

Original language	English
Title of host publication	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	49-50
Number of pages	2
ISBN (Electronic)	0780350081
DOIs	https://doi.org/10.1109/ICECS.1998.814820
State	Published - 1998
Event	5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998 - Lisboa, Portugal Duration: 7 Sep 1998 → 10 Sep 1998

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume	2

Conference

Conference	5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998
Country/Territory	Portugal
City	Lisboa
Period	7/09/98 → 10/09/98

Access to Document

10.1109/ICECS.1998.814820

Cite this

Cheng, K. H., Yeha, Y. K., & Lian, F. S. (1998). Low voltage low power high-speed BiCMOS multiplier. In Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (pp. 49-50). Article 814820 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 2). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.1998.814820

@inproceedings{949b4171d10547898b6a71e2110a3358,

title = "Low voltage low power high-speed BiCMOS multiplier",

abstract = "A 16×16-bit parallel multiplier fabricated in a 1.0 μm BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth's algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 μW at 2.5 V supply voltage operation.",

author = "Cheng, {Kuo Hsing} and Yeha, {Yu Kwang} and Lian, {Farn Sou}",

note = "Publisher Copyright: {\textcopyright} 1998 IEEE.; 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998 ; Conference date: 07-09-1998 Through 10-09-1998",

year = "1998",

doi = "10.1109/ICECS.1998.814820",

language = "???core.languages.en_GB???",

series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "49--50",

booktitle = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

}

Cheng, KH, Yeha, YK & Lian, FS 1998, Low voltage low power high-speed BiCMOS multiplier. in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems., 814820, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 2, Institute of Electrical and Electronics Engineers Inc., pp. 49-50, 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, Lisboa, Portugal, 7/09/98. https://doi.org/10.1109/ICECS.1998.814820

Low voltage low power high-speed BiCMOS multiplier. / Cheng, Kuo Hsing; Yeha, Yu Kwang; Lian, Farn Sou.
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems. Institute of Electrical and Electronics Engineers Inc., 1998. p. 49-50 814820 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Low voltage low power high-speed BiCMOS multiplier

AU - Cheng, Kuo Hsing

AU - Yeha, Yu Kwang

AU - Lian, Farn Sou

PY - 1998

Y1 - 1998

N2 - A 16×16-bit parallel multiplier fabricated in a 1.0 μm BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth's algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 μW at 2.5 V supply voltage operation.

AB - A 16×16-bit parallel multiplier fabricated in a 1.0 μm BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth's algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 μW at 2.5 V supply voltage operation.

UR - http://www.scopus.com/inward/record.url?scp=46449123164&partnerID=8YFLogxK

U2 - 10.1109/ICECS.1998.814820

DO - 10.1109/ICECS.1998.814820

M3 - 會議論文篇章

AN - SCOPUS:46449123164

T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

SP - 49

EP - 50

BT - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998

Y2 - 7 September 1998 through 10 September 1998

ER -

Cheng KH, Yeha YK, Lian FS. Low voltage low power high-speed BiCMOS multiplier. In Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems. Institute of Electrical and Electronics Engineers Inc. 1998. p. 49-50. 814820. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). doi: 10.1109/ICECS.1998.814820

Low voltage low power high-speed BiCMOS multiplier

Abstract

Publication series

Conference

Access to Document

Fingerprint

Cite this