Low-voltage low-power CMOS true-single-phase clocking scheme with locally asynchronous logic circuits

Keyphrases

• Low Power CMOS 100%
• Logic Circuit 100%
• Differential Logic 100%
• Asynchronous Circuits 100%
• Clocking Scheme 100%
• Power Dissipation 50%
• Global Clock 50%
• Low Voltage 25%
• Single Gate 25%
• Power Performance 25%
• Low Power 25%
• Complex Function 25%
• Speed-power 25%
• Operation Speed 25%
• Noise Effects 25%
• Pre-charge 25%
• Clock System 25%
• True Single Phase Clock 25%
• Line Noise 25%
• Transient Noise 25%
• Clock Lines 25%

Computer Science

• Clocking Scheme 100%
• Energy Dissipation 66%
• Supply Voltage 33%
• And Gate 33%
• Complex Function 33%
• System Clock 33%

Engineering

• Logic Circuit 100%
• Energy Dissipation 40%
• Simulation Result 20%
• Supply Voltage 20%
• Transients 20%
• Speed Operation 20%
• System Clock 20%
• Induced Noise 20%