Low Routing Complexity Multiframe Pipelined LDPC Decoder Based on a Novel Pseudo Marginalized Min-Sum Algorithm for High Throughput Applications

Keyphrases

• Proposed Design 100%
• Decoder 100%
• Multi-frame 100%
• High-speed Applications 100%
• Low-density Parity-check Codes 100%
• Min-Sum 100%
• Min-max Algorithm 100%
• High-throughput 66%
• Design Basis 66%
• Route Network 66%
• Normalized Min-sum Algorithm 66%
• Codeword 33%
• Bit Error Rate 33%
• Power Consumption 33%
• Low Power Consumption 33%
• CMOS Process 33%
• Code Rate 33%
• Hardware Complexity 33%
• Message Passing 33%
• IEEE 802.11ax 33%
• Implementation Results 33%
• Wirelength 33%
• Rate Requirement 33%
• Quadrature 33%
• Area Consumption 33%
• FinFET CMOS 33%
• 28 Nm CMOS 33%
• Decoder Design 33%
• Application Standard 33%
• Multiple Coding 33%

Computer Science

• High Throughput 100%
• min-sum algorithm 100%
• Network Routing 33%
• Pipelining 16%
• Low Power Consumption 16%
• Power Consumption 16%
• Message-Passing Approach 16%
• Longest Codeword 16%
• Computer Hardware 16%

Engineering

• Network Routing 100%
• Bit Error Rate 50%
• Electric Power Utilization 50%
• Low Power Consumption 50%
• Hardware Complexity 50%