Low power multi-lane MIPI CSI-2 receiver design and hardware implementations

Yueh Chuan Lu, Zong Yi Chen, Pao Chi Chang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

This paper proposes a low power multi-Lane Mobile Industry Processor Interface (MIPI) Camera Serial Interface 2 (CSI-2) receiver architecture which adopts an 8-Byte parallel CSI protocol layer for hardware implementations. The proposed scheme can work in environment with 4 data Lanes and 1 Gb/s per data Lane, i.e. with maximum data rate 4 Gb/s, at 62.5 MHz which increases logic operations from 8 ns (125 MHz) to 16 ns (62.5 MHz) without throughput degradation. Therefore, the supply voltage (1.2 V) can be reduced and the power consumption can also be reduced. The proposed architecture is implemented by 0.13μm CMOS technology and the total gate count is 32.7K. It not only reduces the operating clock rate but also reduces more than 37%∼43% logic power consumption measured in chip.

Original languageEnglish
Title of host publication2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013
Pages199-200
Number of pages2
DOIs
StatePublished - 2013
Event2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013 - Hsinchu, Taiwan
Duration: 3 Jun 20136 Jun 2013

Publication series

NameProceedings of the International Symposium on Consumer Electronics, ISCE

Conference

Conference2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013
Country/TerritoryTaiwan
CityHsinchu
Period3/06/136/06/13

Fingerprint

Dive into the research topics of 'Low power multi-lane MIPI CSI-2 receiver design and hardware implementations'. Together they form a unique fingerprint.

Cite this