Low power architecture design and hardware implementations of deblocking filter in H.264/AVC

Hua Chang Chung, Zong Yi Chen, Pao Chi Chang

Research output: Contribution to journalArticlepeer-review

14 Scopus citations

Abstract

An adaptive in-loop deblocking filter (DF) is standardized in H.264/AVC to reduce blocking artifacts and improve compression efficiency. This paper proposes a low power DF architecture with hybrid and intelligent edge skip filtering order. We further adopt a four-stage pipeline to boost the speed of DF process and the proposed Horizontal Edge Skip Processing Architecture (HESPA) offers an edge skip aware mechanism for filtering the horizontal edges that not only reduces power consumption but also reduces the filtering processes down to 100 clock cycles per macroblock (MB). In addition, the architecture utilizes the buffers efficiently to store the temporary data without affecting the standarddefined data dependency by a reasonable strategy of edge filtering order to enhance the reusability of the intermediate data. The system throughput can then be improved and the power consumption can also be reduced. Simulation results show that more than 34% of logic power measured in FPGA can be saved when the proposed HESPA is enabled. Furthermore, the proposed architecture is implemented on a 0.18 μm standard cell library, which consumes 19.8K gates at a clock frequency of 200 MHz, which compares competitively with other state-of-the-art works in terms of hardware cost.

Original languageEnglish
Article number5955212
Pages (from-to)713-719
Number of pages7
JournalIEEE Transactions on Consumer Electronics
Volume57
Issue number2
DOIs
StatePublished - May 2011

Keywords

  • Deblocking Filter
  • Design
  • FPGA
  • H.264/AVC
  • Hardware Implementation
  • Low Power

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