TY - JOUR
T1 - Low power and cost effective VLSI design for an MP3 audio decoder using an optimised synthesis-subband approach
AU - Tsai, T. H.
AU - Yang, Y. C.
PY - 2004/5
Y1 - 2004/5
N2 - An optimised approach to MPEG layer-3 (MP3) audio decoding is presented, with the main theme focused on the synthesis subband. Since the synthesis subband is the most power-consuming component in decoding, a cost-effective architecture is proposed based on a system-design consideration. By means of an algorithm and architecture, the synthesis subband achieves a high throughput with reduced memory requirements and hardware complexity. With a two-stage pipeline architecture, it allows 100% hardware utilisation and is suitable for low-power implementation. In addition, the chip design in a 0.35 μm process is also accomplished. It occupies a die area of about 2.7 × 3.2 mm2 with a transistor count of 157469 and a low-power dissipation of only 2.92 mW.
AB - An optimised approach to MPEG layer-3 (MP3) audio decoding is presented, with the main theme focused on the synthesis subband. Since the synthesis subband is the most power-consuming component in decoding, a cost-effective architecture is proposed based on a system-design consideration. By means of an algorithm and architecture, the synthesis subband achieves a high throughput with reduced memory requirements and hardware complexity. With a two-stage pipeline architecture, it allows 100% hardware utilisation and is suitable for low-power implementation. In addition, the chip design in a 0.35 μm process is also accomplished. It occupies a die area of about 2.7 × 3.2 mm2 with a transistor count of 157469 and a low-power dissipation of only 2.92 mW.
UR - http://www.scopus.com/inward/record.url?scp=2942752401&partnerID=8YFLogxK
U2 - 10.1049/ip-cdt:20040486
DO - 10.1049/ip-cdt:20040486
M3 - 期刊論文
AN - SCOPUS:2942752401
SN - 1350-2387
VL - 151
SP - 245
EP - 251
JO - IEE Proceedings: Computers and Digital Techniques
JF - IEE Proceedings: Computers and Digital Techniques
IS - 3
ER -