Low-jitter and low-power phase-locked loop design

Keyphrases

• Low Power 100%
• Low Jitter 100%
• Phase-locked Loop 100%
• Digital Phase-locked Loop 100%
• Loop Design 100%
• Low Power Consumption 66%
• Voltage-controlled Oscillator 66%
• Phase Frequency Detector 66%
• Phase Error 33%
• Supply Voltage 33%
• CMOS Technology 33%
• Power Consumption 33%
• Result-oriented 33%
• Dead Zone 33%
• Jitter 33%
• Output Frequency 33%
• Oscillator Frequency 33%
• Total Energy Consumption 33%
• Three-state 33%
• State Structure 33%
• Long-term Jitter 33%

Engineering

• Phase Locked Loop 100%
• Electric Power Utilization 50%
• Low Power Consumption 50%
• Voltage-Controlled Oscillator 50%
• Phase Error 25%
• Supply Voltage 25%
• Output Frequency 25%
• Oscillator 25%