Low-jitter and low-power phase-locked loop design

Kuo Hsing Chen; Huan Sen Liao; Lin Jiunn Tzou

doi:10.1109/ISCAS.2000.856310

Low-jitter and low-power phase-locked loop design

Kuo Hsing Chen, Huan Sen Liao, Lin Jiunn Tzou

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

8 Scopus citations

Abstract

This paper describes a design of digital phase-locked loop (DPLL), which has low-power consumption and low jitter feature. Novel voltage controlled oscillator (VCO) and phase frequency detector (PFD) are proposed to reduce the total power consumption and phase error of the DPLL. The proposed VCO has low power consumption, and the PFD is a `three-state' structure with dead zone is 5 ps. The power consumption of the proposed DPLL is lower than 6.7 mW, and the output-frequency range of the oscillator is from 200 MHz to 650 MHz. The worst-case cycle jitter is lower than 160 ps, and long-term jitter is lower than 220 ps. We confirm the results based on 0.5 um CMOS technology and 3 V supply voltage.

Original language	English
Pages (from-to)	II-257-II-260
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2
DOIs	https://doi.org/10.1109/ISCAS.2000.856310
State	Published - 2000
Event	Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 - Geneva, Switz, Switzerland Duration: 28 May 2000 → 31 May 2000

Access to Document

10.1109/ISCAS.2000.856310

Cite this

@article{30dc39c1136c482a8d328024c9e338c4,

title = "Low-jitter and low-power phase-locked loop design",

abstract = "This paper describes a design of digital phase-locked loop (DPLL), which has low-power consumption and low jitter feature. Novel voltage controlled oscillator (VCO) and phase frequency detector (PFD) are proposed to reduce the total power consumption and phase error of the DPLL. The proposed VCO has low power consumption, and the PFD is a `three-state' structure with dead zone is 5 ps. The power consumption of the proposed DPLL is lower than 6.7 mW, and the output-frequency range of the oscillator is from 200 MHz to 650 MHz. The worst-case cycle jitter is lower than 160 ps, and long-term jitter is lower than 220 ps. We confirm the results based on 0.5 um CMOS technology and 3 V supply voltage.",

author = "Chen, {Kuo Hsing} and Liao, {Huan Sen} and Tzou, {Lin Jiunn}",

year = "2000",

doi = "10.1109/ISCAS.2000.856310",

language = "???core.languages.en_GB???",

volume = "2",

pages = "II--257--II--260",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

note = "Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 ; Conference date: 28-05-2000 Through 31-05-2000",

}

TY - JOUR

T1 - Low-jitter and low-power phase-locked loop design

AU - Chen, Kuo Hsing

AU - Liao, Huan Sen

AU - Tzou, Lin Jiunn

PY - 2000

Y1 - 2000

N2 - This paper describes a design of digital phase-locked loop (DPLL), which has low-power consumption and low jitter feature. Novel voltage controlled oscillator (VCO) and phase frequency detector (PFD) are proposed to reduce the total power consumption and phase error of the DPLL. The proposed VCO has low power consumption, and the PFD is a `three-state' structure with dead zone is 5 ps. The power consumption of the proposed DPLL is lower than 6.7 mW, and the output-frequency range of the oscillator is from 200 MHz to 650 MHz. The worst-case cycle jitter is lower than 160 ps, and long-term jitter is lower than 220 ps. We confirm the results based on 0.5 um CMOS technology and 3 V supply voltage.

AB - This paper describes a design of digital phase-locked loop (DPLL), which has low-power consumption and low jitter feature. Novel voltage controlled oscillator (VCO) and phase frequency detector (PFD) are proposed to reduce the total power consumption and phase error of the DPLL. The proposed VCO has low power consumption, and the PFD is a `three-state' structure with dead zone is 5 ps. The power consumption of the proposed DPLL is lower than 6.7 mW, and the output-frequency range of the oscillator is from 200 MHz to 650 MHz. The worst-case cycle jitter is lower than 160 ps, and long-term jitter is lower than 220 ps. We confirm the results based on 0.5 um CMOS technology and 3 V supply voltage.

UR - http://www.scopus.com/inward/record.url?scp=0033681625&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2000.856310

DO - 10.1109/ISCAS.2000.856310

M3 - 會議論文

AN - SCOPUS:0033681625

SN - 0271-4310

VL - 2

SP - II-257-II-260

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000

Y2 - 28 May 2000 through 31 May 2000

ER -

Low-jitter and low-power phase-locked loop design

Abstract

Access to Document

Fingerprint

Cite this