Low-cost BISDC design for motion estimation computing array

Chang Hsin Cheng, Yu Liu, Chun Lung Hsu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper develops a built-in self-detecting / correcting (BISDC) architecture design for motion estimation computing array (MECA). Based on the error-detecting / correcting concepts of low cost remainder and quotient (RQ) arithmetic codes, any error of each processing element (PE) in MECA can be effectively detected and corrected on-line by using the proposed built-in self-detecting (BISD) and built-in selfcorrecting (BISC) circuits, respectively. Performance analysis and evaluation show the proposed BISDC architecture has little area overhead and timing penalty.

Original languageEnglish
Title of host publication2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09
DOIs
StatePublished - 2009
Event2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09 - Chengdu, China
Duration: 28 Apr 200929 Apr 2009

Publication series

Name2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09

Conference

Conference2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09
Country/TerritoryChina
CityChengdu
Period28/04/0929/04/09

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