Low-cost BISDC design for motion estimation computing array

Chang Hsin Cheng; Yu Liu; Chun Lung Hsu

doi:10.1109/CAS-ICTD.2009.4960835

Low-cost BISDC design for motion estimation computing array

Chang Hsin Cheng, Yu Liu, Chun Lung Hsu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper develops a built-in self-detecting / correcting (BISDC) architecture design for motion estimation computing array (MECA). Based on the error-detecting / correcting concepts of low cost remainder and quotient (RQ) arithmetic codes, any error of each processing element (PE) in MECA can be effectively detected and corrected on-line by using the proposed built-in self-detecting (BISD) and built-in selfcorrecting (BISC) circuits, respectively. Performance analysis and evaluation show the proposed BISDC architecture has little area overhead and timing penalty.

Original language	English
Title of host publication	2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09
DOIs	https://doi.org/10.1109/CAS-ICTD.2009.4960835
State	Published - 2009
Event	2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09 - Chengdu, China Duration: 28 Apr 2009 → 29 Apr 2009

Publication series

Name	2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09

Conference

Conference	2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09
Country/Territory	China
City	Chengdu
Period	28/04/09 → 29/04/09

Access to Document

10.1109/CAS-ICTD.2009.4960835

Cite this

@inproceedings{2ad9713ca6c6444caa4b0542432ee44c,

title = "Low-cost BISDC design for motion estimation computing array",

abstract = "This paper develops a built-in self-detecting / correcting (BISDC) architecture design for motion estimation computing array (MECA). Based on the error-detecting / correcting concepts of low cost remainder and quotient (RQ) arithmetic codes, any error of each processing element (PE) in MECA can be effectively detected and corrected on-line by using the proposed built-in self-detecting (BISD) and built-in selfcorrecting (BISC) circuits, respectively. Performance analysis and evaluation show the proposed BISDC architecture has little area overhead and timing penalty.",

author = "Cheng, {Chang Hsin} and Yu Liu and Hsu, {Chun Lung}",

year = "2009",

doi = "10.1109/CAS-ICTD.2009.4960835",

language = "???core.languages.en_GB???",

isbn = "9781424425877",

series = "2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09",

booktitle = "2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09",

note = "2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09 ; Conference date: 28-04-2009 Through 29-04-2009",

}

Cheng, CH, Liu, Y & Hsu, CL 2009, Low-cost BISDC design for motion estimation computing array. in 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09., 4960835, 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09, 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09, Chengdu, China, 28/04/09. https://doi.org/10.1109/CAS-ICTD.2009.4960835

Low-cost BISDC design for motion estimation computing array. / Cheng, Chang Hsin; Liu, Yu; Hsu, Chun Lung.
2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09. 2009. 4960835 (2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Low-cost BISDC design for motion estimation computing array

AU - Cheng, Chang Hsin

AU - Liu, Yu

AU - Hsu, Chun Lung

PY - 2009

Y1 - 2009

N2 - This paper develops a built-in self-detecting / correcting (BISDC) architecture design for motion estimation computing array (MECA). Based on the error-detecting / correcting concepts of low cost remainder and quotient (RQ) arithmetic codes, any error of each processing element (PE) in MECA can be effectively detected and corrected on-line by using the proposed built-in self-detecting (BISD) and built-in selfcorrecting (BISC) circuits, respectively. Performance analysis and evaluation show the proposed BISDC architecture has little area overhead and timing penalty.

AB - This paper develops a built-in self-detecting / correcting (BISDC) architecture design for motion estimation computing array (MECA). Based on the error-detecting / correcting concepts of low cost remainder and quotient (RQ) arithmetic codes, any error of each processing element (PE) in MECA can be effectively detected and corrected on-line by using the proposed built-in self-detecting (BISD) and built-in selfcorrecting (BISC) circuits, respectively. Performance analysis and evaluation show the proposed BISDC architecture has little area overhead and timing penalty.

UR - http://www.scopus.com/inward/record.url?scp=70149099550&partnerID=8YFLogxK

U2 - 10.1109/CAS-ICTD.2009.4960835

DO - 10.1109/CAS-ICTD.2009.4960835

M3 - 會議論文篇章

AN - SCOPUS:70149099550

SN - 9781424425877

T3 - 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09

BT - 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09

T2 - 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09

Y2 - 28 April 2009 through 29 April 2009

ER -

Low-cost BISDC design for motion estimation computing array

Abstract

Publication series

Conference

Access to Document

Fingerprint

Cite this