Low-cost architecture design with efficient data arrangement and memory configuration for MPEG-2 audio decoder

Tsung Han Tsai; Liang Gee Chen; Sheng Chieh Huang; Hao Chieh Chang

Low-cost architecture design with efficient data arrangement and memory configuration for MPEG-2 audio decoder

Tsung Han Tsai, Liang Gee Chen, Sheng Chieh Huang, Hao Chieh Chang

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

1 Scopus citations

Abstract

The paper describes a low-cost MPEG-2 audio decoder with a modified fast algorithm for decoding. In the modified decoding scheme, the computation amount of the bottleneck module can be reduced into one-fourths of the original one. Also, the major memory storage only requires half size of the standard synthesis subband filterbank. The decoder is developed for the approaches of simplicity and low-cost architecture design, with the techniques of intelligent data arrangement and memory configuration.

Original language	English
Pages (from-to)	65-68
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	4
State	Published - 1998
Event	Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA Duration: 31 May 1998 → 3 Jun 1998

Cite this

@article{b29b5153da0b443bb73ecfbe228ed71c,

title = "Low-cost architecture design with efficient data arrangement and memory configuration for MPEG-2 audio decoder",

abstract = "The paper describes a low-cost MPEG-2 audio decoder with a modified fast algorithm for decoding. In the modified decoding scheme, the computation amount of the bottleneck module can be reduced into one-fourths of the original one. Also, the major memory storage only requires half size of the standard synthesis subband filterbank. The decoder is developed for the approaches of simplicity and low-cost architecture design, with the techniques of intelligent data arrangement and memory configuration.",

author = "Tsai, {Tsung Han} and Chen, {Liang Gee} and Huang, {Sheng Chieh} and Chang, {Hao Chieh}",

year = "1998",

language = "???core.languages.en_GB???",

volume = "4",

pages = "65--68",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

note = "Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) ; Conference date: 31-05-1998 Through 03-06-1998",

}

TY - JOUR

T1 - Low-cost architecture design with efficient data arrangement and memory configuration for MPEG-2 audio decoder

AU - Tsai, Tsung Han

AU - Chen, Liang Gee

AU - Huang, Sheng Chieh

AU - Chang, Hao Chieh

PY - 1998

Y1 - 1998

N2 - The paper describes a low-cost MPEG-2 audio decoder with a modified fast algorithm for decoding. In the modified decoding scheme, the computation amount of the bottleneck module can be reduced into one-fourths of the original one. Also, the major memory storage only requires half size of the standard synthesis subband filterbank. The decoder is developed for the approaches of simplicity and low-cost architecture design, with the techniques of intelligent data arrangement and memory configuration.

AB - The paper describes a low-cost MPEG-2 audio decoder with a modified fast algorithm for decoding. In the modified decoding scheme, the computation amount of the bottleneck module can be reduced into one-fourths of the original one. Also, the major memory storage only requires half size of the standard synthesis subband filterbank. The decoder is developed for the approaches of simplicity and low-cost architecture design, with the techniques of intelligent data arrangement and memory configuration.

UR - http://www.scopus.com/inward/record.url?scp=0031622643&partnerID=8YFLogxK

M3 - 會議論文

AN - SCOPUS:0031622643

SN - 0271-4310

VL - 4

SP - 65

EP - 68

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6)

Y2 - 31 May 1998 through 3 June 1998

ER -

Low-cost architecture design with efficient data arrangement and memory configuration for MPEG-2 audio decoder

Abstract

Fingerprint

Cite this